1062ef1a6SPriyanka Jain /* 2062ef1a6SPriyanka Jain * Copyright 2013 Freescale Semiconductor, Inc. 3062ef1a6SPriyanka Jain * 4062ef1a6SPriyanka Jain * SPDX-License-Identifier: GPL-2.0+ 5062ef1a6SPriyanka Jain */ 6062ef1a6SPriyanka Jain 7062ef1a6SPriyanka Jain #include <common.h> 8062ef1a6SPriyanka Jain #include <asm/mmu.h> 9062ef1a6SPriyanka Jain 10062ef1a6SPriyanka Jain struct fsl_e_tlb_entry tlb_table[] = { 11062ef1a6SPriyanka Jain /* TLB 0 - for temp stack in cache */ 12062ef1a6SPriyanka Jain SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, 13062ef1a6SPriyanka Jain CONFIG_SYS_INIT_RAM_ADDR_PHYS, 14062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, 0, 15062ef1a6SPriyanka Jain 0, 0, BOOKE_PAGESZ_4K, 0), 16062ef1a6SPriyanka Jain SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 17062ef1a6SPriyanka Jain CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, 18062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, 0, 19062ef1a6SPriyanka Jain 0, 0, BOOKE_PAGESZ_4K, 0), 20062ef1a6SPriyanka Jain SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 21062ef1a6SPriyanka Jain CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, 22062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, 0, 23062ef1a6SPriyanka Jain 0, 0, BOOKE_PAGESZ_4K, 0), 24062ef1a6SPriyanka Jain SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 25062ef1a6SPriyanka Jain CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, 26062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, 0, 27062ef1a6SPriyanka Jain 0, 0, BOOKE_PAGESZ_4K, 0), 28062ef1a6SPriyanka Jain 29062ef1a6SPriyanka Jain /* TLB 1 */ 30062ef1a6SPriyanka Jain /* *I*** - Covers boot page */ 31*aa36c84eSSumit Garg #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) && \ 32*aa36c84eSSumit Garg !defined(CONFIG_SECURE_BOOT) 33062ef1a6SPriyanka Jain /* 34062ef1a6SPriyanka Jain * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the 35062ef1a6SPriyanka Jain * SRAM is at 0xfffc0000, it covered the 0xfffff000. 36062ef1a6SPriyanka Jain */ 37062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, 38062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 39062ef1a6SPriyanka Jain 0, 0, BOOKE_PAGESZ_256K, 1), 40*aa36c84eSSumit Garg 41*aa36c84eSSumit Garg #elif defined(CONFIG_SECURE_BOOT) && defined(CONFIG_SPL_BUILD) 42*aa36c84eSSumit Garg /* 43*aa36c84eSSumit Garg * *I*G - L3SRAM. When L3 is used as 256K SRAM, in case of Secure Boot 44*aa36c84eSSumit Garg * the physical address of the SRAM is at 0xbffc0000, 45*aa36c84eSSumit Garg * and virtual address is 0xfffc0000 46*aa36c84eSSumit Garg */ 47*aa36c84eSSumit Garg 48*aa36c84eSSumit Garg SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_VADDR, 49*aa36c84eSSumit Garg CONFIG_SYS_INIT_L3_ADDR, 50*aa36c84eSSumit Garg MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 51*aa36c84eSSumit Garg 0, 0, BOOKE_PAGESZ_256K, 1), 52062ef1a6SPriyanka Jain #else 53062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 54062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 55062ef1a6SPriyanka Jain 0, 0, BOOKE_PAGESZ_4K, 1), 56062ef1a6SPriyanka Jain #endif 57062ef1a6SPriyanka Jain 58062ef1a6SPriyanka Jain /* *I*G* - CCSRBAR */ 59062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 60062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 61062ef1a6SPriyanka Jain 0, 1, BOOKE_PAGESZ_16M, 1), 62062ef1a6SPriyanka Jain 63062ef1a6SPriyanka Jain /* *I*G* - Flash, localbus */ 64062ef1a6SPriyanka Jain /* This will be changed to *I*G* after relocation to RAM. */ 65062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 66062ef1a6SPriyanka Jain MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 67062ef1a6SPriyanka Jain 0, 2, BOOKE_PAGESZ_256M, 1), 68062ef1a6SPriyanka Jain 6918c01445SPrabhakar Kushwaha #ifndef CONFIG_SPL_BUILD 70062ef1a6SPriyanka Jain /* *I*G* - PCI */ 71062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 72062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 73062ef1a6SPriyanka Jain 0, 3, BOOKE_PAGESZ_1G, 1), 74062ef1a6SPriyanka Jain 75062ef1a6SPriyanka Jain /* *I*G* - PCI I/O */ 76062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 77062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 78062ef1a6SPriyanka Jain 0, 4, BOOKE_PAGESZ_256K, 1), 79062ef1a6SPriyanka Jain 80062ef1a6SPriyanka Jain /* Bman/Qman */ 81062ef1a6SPriyanka Jain #ifdef CONFIG_SYS_BMAN_MEM_PHYS 82062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, 83062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, 0, 84062ef1a6SPriyanka Jain 0, 5, BOOKE_PAGESZ_16M, 1), 85062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, 86062ef1a6SPriyanka Jain CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, 87062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 88062ef1a6SPriyanka Jain 0, 6, BOOKE_PAGESZ_16M, 1), 89062ef1a6SPriyanka Jain #endif 90062ef1a6SPriyanka Jain #ifdef CONFIG_SYS_QMAN_MEM_PHYS 91062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, 92062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, 0, 93062ef1a6SPriyanka Jain 0, 7, BOOKE_PAGESZ_16M, 1), 94062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, 95062ef1a6SPriyanka Jain CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, 96062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 97062ef1a6SPriyanka Jain 0, 8, BOOKE_PAGESZ_16M, 1), 98062ef1a6SPriyanka Jain #endif 9918c01445SPrabhakar Kushwaha #endif 100062ef1a6SPriyanka Jain #ifdef CONFIG_SYS_DCSRBAR_PHYS 101062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, 102062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 103062ef1a6SPriyanka Jain 0, 9, BOOKE_PAGESZ_4M, 1), 104062ef1a6SPriyanka Jain #endif 105062ef1a6SPriyanka Jain #ifdef CONFIG_SYS_NAND_BASE 106062ef1a6SPriyanka Jain /* 107062ef1a6SPriyanka Jain * *I*G - NAND 108062ef1a6SPriyanka Jain * entry 14 and 15 has been used hard coded, they will be disabled 109062ef1a6SPriyanka Jain * in cpu_init_f, so we use entry 16 for nand. 110062ef1a6SPriyanka Jain */ 111062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 112062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 113062ef1a6SPriyanka Jain 0, 10, BOOKE_PAGESZ_64K, 1), 114062ef1a6SPriyanka Jain #endif 115062ef1a6SPriyanka Jain #ifdef CONFIG_SYS_CPLD_BASE 116062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, 117062ef1a6SPriyanka Jain MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 118062ef1a6SPriyanka Jain 0, 11, BOOKE_PAGESZ_256K, 1), 119062ef1a6SPriyanka Jain #endif 12018c01445SPrabhakar Kushwaha 12118c01445SPrabhakar Kushwaha #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) 12218c01445SPrabhakar Kushwaha SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, 12318c01445SPrabhakar Kushwaha MAS3_SX|MAS3_SW|MAS3_SR, 0, 12418c01445SPrabhakar Kushwaha 0, 12, BOOKE_PAGESZ_1G, 1), 12518c01445SPrabhakar Kushwaha SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, 12618c01445SPrabhakar Kushwaha CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, 12718c01445SPrabhakar Kushwaha MAS3_SX|MAS3_SW|MAS3_SR, 0, 12818c01445SPrabhakar Kushwaha 0, 13, BOOKE_PAGESZ_1G, 1) 12918c01445SPrabhakar Kushwaha #endif 130062ef1a6SPriyanka Jain }; 131062ef1a6SPriyanka Jain 132062ef1a6SPriyanka Jain int num_tlb_entries = ARRAY_SIZE(tlb_table); 133