1062ef1a6SPriyanka Jain /* 2062ef1a6SPriyanka Jain * Copyright 2013 Freescale Semiconductor, Inc. 3062ef1a6SPriyanka Jain * 4062ef1a6SPriyanka Jain * SPDX-License-Identifier: GPL-2.0+ 5062ef1a6SPriyanka Jain */ 6062ef1a6SPriyanka Jain 7062ef1a6SPriyanka Jain #include <common.h> 8062ef1a6SPriyanka Jain #include <asm/mmu.h> 9062ef1a6SPriyanka Jain 10062ef1a6SPriyanka Jain struct fsl_e_tlb_entry tlb_table[] = { 11062ef1a6SPriyanka Jain /* TLB 0 - for temp stack in cache */ 12062ef1a6SPriyanka Jain SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, 13062ef1a6SPriyanka Jain CONFIG_SYS_INIT_RAM_ADDR_PHYS, 14062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, 0, 15062ef1a6SPriyanka Jain 0, 0, BOOKE_PAGESZ_4K, 0), 16062ef1a6SPriyanka Jain SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 17062ef1a6SPriyanka Jain CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, 18062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, 0, 19062ef1a6SPriyanka Jain 0, 0, BOOKE_PAGESZ_4K, 0), 20062ef1a6SPriyanka Jain SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 21062ef1a6SPriyanka Jain CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, 22062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, 0, 23062ef1a6SPriyanka Jain 0, 0, BOOKE_PAGESZ_4K, 0), 24062ef1a6SPriyanka Jain SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 25062ef1a6SPriyanka Jain CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, 26062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, 0, 27062ef1a6SPriyanka Jain 0, 0, BOOKE_PAGESZ_4K, 0), 28062ef1a6SPriyanka Jain 29062ef1a6SPriyanka Jain /* TLB 1 */ 30062ef1a6SPriyanka Jain /* *I*** - Covers boot page */ 31062ef1a6SPriyanka Jain #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) 32062ef1a6SPriyanka Jain /* 33062ef1a6SPriyanka Jain * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the 34062ef1a6SPriyanka Jain * SRAM is at 0xfffc0000, it covered the 0xfffff000. 35062ef1a6SPriyanka Jain */ 36062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, 37062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 38062ef1a6SPriyanka Jain 0, 0, BOOKE_PAGESZ_256K, 1), 39062ef1a6SPriyanka Jain #else 40062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 41062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 42062ef1a6SPriyanka Jain 0, 0, BOOKE_PAGESZ_4K, 1), 43062ef1a6SPriyanka Jain #endif 44062ef1a6SPriyanka Jain 45062ef1a6SPriyanka Jain /* *I*G* - CCSRBAR */ 46062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 47062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 48062ef1a6SPriyanka Jain 0, 1, BOOKE_PAGESZ_16M, 1), 49062ef1a6SPriyanka Jain 50062ef1a6SPriyanka Jain /* *I*G* - Flash, localbus */ 51062ef1a6SPriyanka Jain /* This will be changed to *I*G* after relocation to RAM. */ 52062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 53062ef1a6SPriyanka Jain MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 54062ef1a6SPriyanka Jain 0, 2, BOOKE_PAGESZ_256M, 1), 55062ef1a6SPriyanka Jain 56*18c01445SPrabhakar Kushwaha #ifndef CONFIG_SPL_BUILD 57062ef1a6SPriyanka Jain /* *I*G* - PCI */ 58062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 59062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 60062ef1a6SPriyanka Jain 0, 3, BOOKE_PAGESZ_1G, 1), 61062ef1a6SPriyanka Jain 62062ef1a6SPriyanka Jain /* *I*G* - PCI I/O */ 63062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 64062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 65062ef1a6SPriyanka Jain 0, 4, BOOKE_PAGESZ_256K, 1), 66062ef1a6SPriyanka Jain 67062ef1a6SPriyanka Jain /* Bman/Qman */ 68062ef1a6SPriyanka Jain #ifdef CONFIG_SYS_BMAN_MEM_PHYS 69062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, 70062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, 0, 71062ef1a6SPriyanka Jain 0, 5, BOOKE_PAGESZ_16M, 1), 72062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, 73062ef1a6SPriyanka Jain CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, 74062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 75062ef1a6SPriyanka Jain 0, 6, BOOKE_PAGESZ_16M, 1), 76062ef1a6SPriyanka Jain #endif 77062ef1a6SPriyanka Jain #ifdef CONFIG_SYS_QMAN_MEM_PHYS 78062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, 79062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, 0, 80062ef1a6SPriyanka Jain 0, 7, BOOKE_PAGESZ_16M, 1), 81062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, 82062ef1a6SPriyanka Jain CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, 83062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 84062ef1a6SPriyanka Jain 0, 8, BOOKE_PAGESZ_16M, 1), 85062ef1a6SPriyanka Jain #endif 86*18c01445SPrabhakar Kushwaha #endif 87062ef1a6SPriyanka Jain #ifdef CONFIG_SYS_DCSRBAR_PHYS 88062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, 89062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 90062ef1a6SPriyanka Jain 0, 9, BOOKE_PAGESZ_4M, 1), 91062ef1a6SPriyanka Jain #endif 92062ef1a6SPriyanka Jain #ifdef CONFIG_SYS_NAND_BASE 93062ef1a6SPriyanka Jain /* 94062ef1a6SPriyanka Jain * *I*G - NAND 95062ef1a6SPriyanka Jain * entry 14 and 15 has been used hard coded, they will be disabled 96062ef1a6SPriyanka Jain * in cpu_init_f, so we use entry 16 for nand. 97062ef1a6SPriyanka Jain */ 98062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 99062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 100062ef1a6SPriyanka Jain 0, 10, BOOKE_PAGESZ_64K, 1), 101062ef1a6SPriyanka Jain #endif 102062ef1a6SPriyanka Jain #ifdef CONFIG_SYS_CPLD_BASE 103062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, 104062ef1a6SPriyanka Jain MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 105062ef1a6SPriyanka Jain 0, 11, BOOKE_PAGESZ_256K, 1), 106062ef1a6SPriyanka Jain #endif 107*18c01445SPrabhakar Kushwaha 108*18c01445SPrabhakar Kushwaha #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) 109*18c01445SPrabhakar Kushwaha SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, 110*18c01445SPrabhakar Kushwaha MAS3_SX|MAS3_SW|MAS3_SR, 0, 111*18c01445SPrabhakar Kushwaha 0, 12, BOOKE_PAGESZ_1G, 1), 112*18c01445SPrabhakar Kushwaha SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, 113*18c01445SPrabhakar Kushwaha CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, 114*18c01445SPrabhakar Kushwaha MAS3_SX|MAS3_SW|MAS3_SR, 0, 115*18c01445SPrabhakar Kushwaha 0, 13, BOOKE_PAGESZ_1G, 1) 116*18c01445SPrabhakar Kushwaha #endif 117062ef1a6SPriyanka Jain }; 118062ef1a6SPriyanka Jain 119062ef1a6SPriyanka Jain int num_tlb_entries = ARRAY_SIZE(tlb_table); 120