1*062ef1a6SPriyanka Jain /* 2*062ef1a6SPriyanka Jain * Copyright 2013 Freescale Semiconductor, Inc. 3*062ef1a6SPriyanka Jain * 4*062ef1a6SPriyanka Jain * SPDX-License-Identifier: GPL-2.0+ 5*062ef1a6SPriyanka Jain */ 6*062ef1a6SPriyanka Jain 7*062ef1a6SPriyanka Jain #include <common.h> 8*062ef1a6SPriyanka Jain #include <asm/mmu.h> 9*062ef1a6SPriyanka Jain 10*062ef1a6SPriyanka Jain struct fsl_e_tlb_entry tlb_table[] = { 11*062ef1a6SPriyanka Jain /* TLB 0 - for temp stack in cache */ 12*062ef1a6SPriyanka Jain SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, 13*062ef1a6SPriyanka Jain CONFIG_SYS_INIT_RAM_ADDR_PHYS, 14*062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, 0, 15*062ef1a6SPriyanka Jain 0, 0, BOOKE_PAGESZ_4K, 0), 16*062ef1a6SPriyanka Jain SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 17*062ef1a6SPriyanka Jain CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, 18*062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, 0, 19*062ef1a6SPriyanka Jain 0, 0, BOOKE_PAGESZ_4K, 0), 20*062ef1a6SPriyanka Jain SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 21*062ef1a6SPriyanka Jain CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, 22*062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, 0, 23*062ef1a6SPriyanka Jain 0, 0, BOOKE_PAGESZ_4K, 0), 24*062ef1a6SPriyanka Jain SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 25*062ef1a6SPriyanka Jain CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, 26*062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, 0, 27*062ef1a6SPriyanka Jain 0, 0, BOOKE_PAGESZ_4K, 0), 28*062ef1a6SPriyanka Jain 29*062ef1a6SPriyanka Jain /* TLB 1 */ 30*062ef1a6SPriyanka Jain /* *I*** - Covers boot page */ 31*062ef1a6SPriyanka Jain #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) 32*062ef1a6SPriyanka Jain /* 33*062ef1a6SPriyanka Jain * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the 34*062ef1a6SPriyanka Jain * SRAM is at 0xfffc0000, it covered the 0xfffff000. 35*062ef1a6SPriyanka Jain */ 36*062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, 37*062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 38*062ef1a6SPriyanka Jain 0, 0, BOOKE_PAGESZ_256K, 1), 39*062ef1a6SPriyanka Jain #else 40*062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 41*062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 42*062ef1a6SPriyanka Jain 0, 0, BOOKE_PAGESZ_4K, 1), 43*062ef1a6SPriyanka Jain #endif 44*062ef1a6SPriyanka Jain 45*062ef1a6SPriyanka Jain /* *I*G* - CCSRBAR */ 46*062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 47*062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 48*062ef1a6SPriyanka Jain 0, 1, BOOKE_PAGESZ_16M, 1), 49*062ef1a6SPriyanka Jain 50*062ef1a6SPriyanka Jain /* *I*G* - Flash, localbus */ 51*062ef1a6SPriyanka Jain /* This will be changed to *I*G* after relocation to RAM. */ 52*062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 53*062ef1a6SPriyanka Jain MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 54*062ef1a6SPriyanka Jain 0, 2, BOOKE_PAGESZ_256M, 1), 55*062ef1a6SPriyanka Jain 56*062ef1a6SPriyanka Jain /* *I*G* - PCI */ 57*062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 58*062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 59*062ef1a6SPriyanka Jain 0, 3, BOOKE_PAGESZ_1G, 1), 60*062ef1a6SPriyanka Jain 61*062ef1a6SPriyanka Jain /* *I*G* - PCI I/O */ 62*062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 63*062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 64*062ef1a6SPriyanka Jain 0, 4, BOOKE_PAGESZ_256K, 1), 65*062ef1a6SPriyanka Jain 66*062ef1a6SPriyanka Jain /* Bman/Qman */ 67*062ef1a6SPriyanka Jain #ifdef CONFIG_SYS_BMAN_MEM_PHYS 68*062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, 69*062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, 0, 70*062ef1a6SPriyanka Jain 0, 5, BOOKE_PAGESZ_16M, 1), 71*062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, 72*062ef1a6SPriyanka Jain CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, 73*062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 74*062ef1a6SPriyanka Jain 0, 6, BOOKE_PAGESZ_16M, 1), 75*062ef1a6SPriyanka Jain #endif 76*062ef1a6SPriyanka Jain #ifdef CONFIG_SYS_QMAN_MEM_PHYS 77*062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, 78*062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, 0, 79*062ef1a6SPriyanka Jain 0, 7, BOOKE_PAGESZ_16M, 1), 80*062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, 81*062ef1a6SPriyanka Jain CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, 82*062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 83*062ef1a6SPriyanka Jain 0, 8, BOOKE_PAGESZ_16M, 1), 84*062ef1a6SPriyanka Jain #endif 85*062ef1a6SPriyanka Jain #ifdef CONFIG_SYS_DCSRBAR_PHYS 86*062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, 87*062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 88*062ef1a6SPriyanka Jain 0, 9, BOOKE_PAGESZ_4M, 1), 89*062ef1a6SPriyanka Jain #endif 90*062ef1a6SPriyanka Jain #ifdef CONFIG_SYS_NAND_BASE 91*062ef1a6SPriyanka Jain /* 92*062ef1a6SPriyanka Jain * *I*G - NAND 93*062ef1a6SPriyanka Jain * entry 14 and 15 has been used hard coded, they will be disabled 94*062ef1a6SPriyanka Jain * in cpu_init_f, so we use entry 16 for nand. 95*062ef1a6SPriyanka Jain */ 96*062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 97*062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 98*062ef1a6SPriyanka Jain 0, 10, BOOKE_PAGESZ_64K, 1), 99*062ef1a6SPriyanka Jain #endif 100*062ef1a6SPriyanka Jain #ifdef CONFIG_SYS_CPLD_BASE 101*062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, 102*062ef1a6SPriyanka Jain MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 103*062ef1a6SPriyanka Jain 0, 11, BOOKE_PAGESZ_256K, 1), 104*062ef1a6SPriyanka Jain #endif 105*062ef1a6SPriyanka Jain }; 106*062ef1a6SPriyanka Jain 107*062ef1a6SPriyanka Jain int num_tlb_entries = ARRAY_SIZE(tlb_table); 108