1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <command.h> 9 #include <hwconfig.h> 10 #include <netdev.h> 11 #include <linux/compiler.h> 12 #include <asm/mmu.h> 13 #include <asm/processor.h> 14 #include <asm/cache.h> 15 #include <asm/immap_85xx.h> 16 #include <asm/fsl_fdt.h> 17 #include <asm/fsl_law.h> 18 #include <asm/fsl_serdes.h> 19 #include <asm/fsl_portals.h> 20 #include <asm/fsl_liodn.h> 21 #include <fm_eth.h> 22 #include "../common/sleep.h" 23 #include "t104xrdb.h" 24 #include "cpld.h" 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 int checkboard(void) 29 { 30 struct cpu_type *cpu = gd->arch.cpu; 31 u8 sw; 32 33 #ifdef CONFIG_T104XD4RDB 34 printf("Board: %sD4RDB\n", cpu->name); 35 #else 36 printf("Board: %sRDB\n", cpu->name); 37 #endif 38 printf("Board rev: 0x%02x CPLD ver: 0x%02x, ", 39 CPLD_READ(hw_ver), CPLD_READ(sw_ver)); 40 41 sw = CPLD_READ(flash_ctl_status); 42 sw = ((sw & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT); 43 44 printf("vBank: %d\n", sw); 45 46 return 0; 47 } 48 49 int board_early_init_f(void) 50 { 51 #if defined(CONFIG_DEEP_SLEEP) 52 if (is_warm_boot()) 53 fsl_dp_disable_console(); 54 #endif 55 56 return 0; 57 } 58 59 int board_early_init_r(void) 60 { 61 #ifdef CONFIG_SYS_FLASH_BASE 62 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 63 int flash_esel = find_tlb_idx((void *)flashbase, 1); 64 65 /* 66 * Remap Boot flash region to caching-inhibited 67 * so that flash can be erased properly. 68 */ 69 70 /* Flush d-cache and invalidate i-cache of any FLASH data */ 71 flush_dcache(); 72 invalidate_icache(); 73 74 if (flash_esel == -1) { 75 /* very unlikely unless something is messed up */ 76 puts("Error: Could not find TLB for FLASH BASE\n"); 77 flash_esel = 2; /* give our best effort to continue */ 78 } else { 79 /* invalidate existing TLB entry for flash */ 80 disable_tlb(flash_esel); 81 } 82 83 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, 84 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 85 0, flash_esel, BOOKE_PAGESZ_256M, 1); 86 #endif 87 set_liodns(); 88 #ifdef CONFIG_SYS_DPAA_QBMAN 89 setup_portals(); 90 #endif 91 92 return 0; 93 } 94 95 int misc_init_r(void) 96 { 97 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 98 u32 srds_s1; 99 100 srds_s1 = in_be32(&gur->rcwsr[4]) >> 24; 101 102 printf("SERDES Reference : 0x%X\n", srds_s1); 103 104 /* select SGMII*/ 105 if (srds_s1 == 0x86) 106 CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) | 107 MISC_CTL_SG_SEL); 108 109 /* select SGMII and Aurora*/ 110 if (srds_s1 == 0x8E) 111 CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) | 112 MISC_CTL_SG_SEL | MISC_CTL_AURORA_SEL); 113 114 #if defined(CONFIG_T1040D4RDB) 115 if (hwconfig("qe-tdm")) { 116 CPLD_WRITE(sfp_ctl_status, CPLD_READ(sfp_ctl_status) | 117 MISC_MUX_QE_TDM); 118 printf("QECSR : 0x%02x, mux to qe-tdm\n", 119 CPLD_READ(sfp_ctl_status)); 120 } 121 /* Mask all CPLD interrupt sources, except QSGMII interrupts */ 122 if (CPLD_READ(sw_ver) < 0x03) { 123 debug("CPLD SW version 0x%02x doesn't support int_mask\n", 124 CPLD_READ(sw_ver)); 125 } else { 126 CPLD_WRITE(int_mask, CPLD_INT_MASK_ALL & 127 ~(CPLD_INT_MASK_QSGMII1 | CPLD_INT_MASK_QSGMII2)); 128 } 129 #endif 130 131 return 0; 132 } 133 134 int ft_board_setup(void *blob, bd_t *bd) 135 { 136 phys_addr_t base; 137 phys_size_t size; 138 139 ft_cpu_setup(blob, bd); 140 141 base = getenv_bootm_low(); 142 size = getenv_bootm_size(); 143 144 fdt_fixup_memory(blob, (u64)base, (u64)size); 145 146 #ifdef CONFIG_PCI 147 pci_of_setup(blob, bd); 148 #endif 149 150 fdt_fixup_liodn(blob); 151 152 #ifdef CONFIG_HAS_FSL_DR_USB 153 fdt_fixup_dr_usb(blob, bd); 154 #endif 155 156 #ifdef CONFIG_SYS_DPAA_FMAN 157 fdt_fixup_fman_ethernet(blob); 158 #endif 159 160 if (hwconfig("qe-tdm")) 161 fdt_del_diu(blob); 162 return 0; 163 } 164