1*18c01445SPrabhakar Kushwaha#PBI commands 2*18c01445SPrabhakar Kushwaha#Initialize CPC1 3*18c01445SPrabhakar Kushwaha09010000 00200400 4*18c01445SPrabhakar Kushwaha09138000 00000000 5*18c01445SPrabhakar Kushwaha091380c0 00000100 6*18c01445SPrabhakar Kushwaha#Configure CPC1 as 256KB SRAM 7*18c01445SPrabhakar Kushwaha09010100 00000000 8*18c01445SPrabhakar Kushwaha09010104 fffc0007 9*18c01445SPrabhakar Kushwaha09010f00 08000000 10*18c01445SPrabhakar Kushwaha09010000 80000000 11*18c01445SPrabhakar Kushwaha#Configure LAW for CPC1 12*18c01445SPrabhakar Kushwaha09000cd0 00000000 13*18c01445SPrabhakar Kushwaha09000cd4 fffc0000 14*18c01445SPrabhakar Kushwaha09000cd8 81000011 15*18c01445SPrabhakar Kushwaha#Configure alternate space 16*18c01445SPrabhakar Kushwaha09000010 00000000 17*18c01445SPrabhakar Kushwaha09000014 ff000000 18*18c01445SPrabhakar Kushwaha09000018 81000000 19*18c01445SPrabhakar Kushwaha#Configure SPI controller 20*18c01445SPrabhakar Kushwaha09110000 80000403 21*18c01445SPrabhakar Kushwaha09110020 2d170008 22*18c01445SPrabhakar Kushwaha09110024 00100008 23*18c01445SPrabhakar Kushwaha09110028 00100008 24*18c01445SPrabhakar Kushwaha0911002c 00100008 25*18c01445SPrabhakar Kushwaha#Flush PBL data 26*18c01445SPrabhakar Kushwaha091380c0 000FFFFF 27