1 /* Copyright 2013 Freescale Semiconductor, Inc. 2 * 3 * SPDX-License-Identifier: GPL-2.0+ 4 */ 5 6 #include <common.h> 7 #include <malloc.h> 8 #include <ns16550.h> 9 #include <nand.h> 10 #include <i2c.h> 11 #include <mmc.h> 12 #include <fsl_esdhc.h> 13 #include <spi_flash.h> 14 #include <asm/mpc85xx_gpio.h> 15 16 DECLARE_GLOBAL_DATA_PTR; 17 18 phys_size_t get_effective_memsize(void) 19 { 20 return CONFIG_SYS_L3_SIZE; 21 } 22 23 unsigned long get_board_sys_clk(void) 24 { 25 return CONFIG_SYS_CLK_FREQ; 26 } 27 28 unsigned long get_board_ddr_clk(void) 29 { 30 return CONFIG_DDR_CLK_FREQ; 31 } 32 33 #define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000 34 void board_init_f(ulong bootflag) 35 { 36 u32 plat_ratio, sys_clk, uart_clk; 37 #ifdef CONFIG_SPL_NAND_BOOT 38 u32 porsr1, pinctl; 39 #endif 40 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 41 42 #ifdef CONFIG_SPL_NAND_BOOT 43 /* 44 * There is T1040 SoC issue where NOR, FPGA are inaccessible during 45 * NAND boot because IFC signals > IFC_AD7 are not enabled. 46 * This workaround changes RCW source to make all signals enabled. 47 */ 48 porsr1 = in_be32(&gur->porsr1); 49 pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000); 50 out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl); 51 #endif 52 53 /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ 54 memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); 55 56 /* Update GD pointer */ 57 gd = (gd_t *)(CONFIG_SPL_GD_ADDR); 58 59 #ifdef CONFIG_DEEP_SLEEP 60 /* disable the console if boot from deep sleep */ 61 if (in_be32(&gur->scrtsr[0]) & (1 << 3)) 62 gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; 63 #endif 64 /* compiler optimization barrier needed for GCC >= 3.4 */ 65 __asm__ __volatile__("" : : : "memory"); 66 67 console_init_f(); 68 69 /* initialize selected port with appropriate baud rate */ 70 sys_clk = get_board_sys_clk(); 71 plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; 72 uart_clk = sys_clk * plat_ratio / 2; 73 74 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, 75 uart_clk / 16 / CONFIG_BAUDRATE); 76 77 relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); 78 } 79 80 void board_init_r(gd_t *gd, ulong dest_addr) 81 { 82 bd_t *bd; 83 84 bd = (bd_t *)(gd + sizeof(gd_t)); 85 memset(bd, 0, sizeof(bd_t)); 86 gd->bd = bd; 87 bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; 88 bd->bi_memsize = CONFIG_SYS_L3_SIZE; 89 90 probecpu(); 91 get_clocks(); 92 mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, 93 CONFIG_SPL_RELOC_MALLOC_SIZE); 94 95 #ifdef CONFIG_SPL_MMC_BOOT 96 mmc_initialize(bd); 97 #endif 98 99 /* relocate environment function pointers etc. */ 100 #ifdef CONFIG_SPL_NAND_BOOT 101 nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, 102 (uchar *)CONFIG_ENV_ADDR); 103 #endif 104 #ifdef CONFIG_SPL_MMC_BOOT 105 mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, 106 (uchar *)CONFIG_ENV_ADDR); 107 #endif 108 #ifdef CONFIG_SPL_SPI_BOOT 109 spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, 110 (uchar *)CONFIG_ENV_ADDR); 111 #endif 112 gd->env_addr = (ulong)(CONFIG_ENV_ADDR); 113 gd->env_valid = 1; 114 115 i2c_init_all(); 116 117 puts("\n\n"); 118 119 gd->ram_size = initdram(0); 120 121 #ifdef CONFIG_SPL_MMC_BOOT 122 mmc_boot(); 123 #elif defined(CONFIG_SPL_SPI_BOOT) 124 spi_boot(); 125 #elif defined(CONFIG_SPL_NAND_BOOT) 126 nand_boot(); 127 #endif 128 } 129 130 #ifdef CONFIG_DEEP_SLEEP 131 void board_mem_sleep_setup(void) 132 { 133 void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE; 134 135 /* does not provide HW signals for power management */ 136 clrbits_8(cpld_base + 0x17, 0x40); 137 /* Disable MCKE isolation */ 138 gpio_set_value(2, 0); 139 udelay(1); 140 } 141 #endif 142