1 /* Copyright 2013 Freescale Semiconductor, Inc. 2 * 3 * SPDX-License-Identifier: GPL-2.0+ 4 */ 5 6 #include <common.h> 7 #include <console.h> 8 #include <malloc.h> 9 #include <ns16550.h> 10 #include <nand.h> 11 #include <i2c.h> 12 #include <mmc.h> 13 #include <fsl_esdhc.h> 14 #include <spi_flash.h> 15 #include "../common/sleep.h" 16 17 DECLARE_GLOBAL_DATA_PTR; 18 19 phys_size_t get_effective_memsize(void) 20 { 21 return CONFIG_SYS_L3_SIZE; 22 } 23 24 unsigned long get_board_sys_clk(void) 25 { 26 return CONFIG_SYS_CLK_FREQ; 27 } 28 29 unsigned long get_board_ddr_clk(void) 30 { 31 return CONFIG_DDR_CLK_FREQ; 32 } 33 34 #define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000 35 void board_init_f(ulong bootflag) 36 { 37 u32 plat_ratio, sys_clk, uart_clk; 38 #if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND) 39 u32 porsr1, pinctl; 40 u32 svr = get_svr(); 41 #endif 42 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 43 44 #if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND) 45 if (IS_SVR_REV(svr, 1, 0)) { 46 /* 47 * There is T1040 SoC issue where NOR, FPGA are inaccessible 48 * during NAND boot because IFC signals > IFC_AD7 are not 49 * enabled. This workaround changes RCW source to make all 50 * signals enabled. 51 */ 52 porsr1 = in_be32(&gur->porsr1); 53 pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) 54 | 0x24800000); 55 out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), 56 pinctl); 57 } 58 #endif 59 60 /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ 61 memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); 62 63 /* Update GD pointer */ 64 gd = (gd_t *)(CONFIG_SPL_GD_ADDR); 65 66 #ifdef CONFIG_DEEP_SLEEP 67 /* disable the console if boot from deep sleep */ 68 if (is_warm_boot()) 69 fsl_dp_disable_console(); 70 #endif 71 /* compiler optimization barrier needed for GCC >= 3.4 */ 72 __asm__ __volatile__("" : : : "memory"); 73 74 console_init_f(); 75 76 /* initialize selected port with appropriate baud rate */ 77 sys_clk = get_board_sys_clk(); 78 plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; 79 uart_clk = sys_clk * plat_ratio / 2; 80 81 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, 82 uart_clk / 16 / CONFIG_BAUDRATE); 83 84 relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); 85 } 86 87 void board_init_r(gd_t *gd, ulong dest_addr) 88 { 89 bd_t *bd; 90 91 bd = (bd_t *)(gd + sizeof(gd_t)); 92 memset(bd, 0, sizeof(bd_t)); 93 gd->bd = bd; 94 bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; 95 bd->bi_memsize = CONFIG_SYS_L3_SIZE; 96 97 probecpu(); 98 get_clocks(); 99 mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, 100 CONFIG_SPL_RELOC_MALLOC_SIZE); 101 gd->flags |= GD_FLG_FULL_MALLOC_INIT; 102 103 #ifdef CONFIG_SPL_MMC_BOOT 104 mmc_initialize(bd); 105 #endif 106 107 /* relocate environment function pointers etc. */ 108 #ifdef CONFIG_SPL_NAND_BOOT 109 nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, 110 (uchar *)CONFIG_ENV_ADDR); 111 #endif 112 #ifdef CONFIG_SPL_MMC_BOOT 113 mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, 114 (uchar *)CONFIG_ENV_ADDR); 115 #endif 116 #ifdef CONFIG_SPL_SPI_BOOT 117 spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, 118 (uchar *)CONFIG_ENV_ADDR); 119 #endif 120 gd->env_addr = (ulong)(CONFIG_ENV_ADDR); 121 gd->env_valid = 1; 122 123 i2c_init_all(); 124 125 puts("\n\n"); 126 127 gd->ram_size = initdram(0); 128 129 #ifdef CONFIG_SPL_MMC_BOOT 130 mmc_boot(); 131 #elif defined(CONFIG_SPL_SPI_BOOT) 132 spi_boot(); 133 #elif defined(CONFIG_SPL_NAND_BOOT) 134 nand_boot(); 135 #endif 136 } 137