118c01445SPrabhakar Kushwaha /* Copyright 2013 Freescale Semiconductor, Inc. 218c01445SPrabhakar Kushwaha * 318c01445SPrabhakar Kushwaha * SPDX-License-Identifier: GPL-2.0+ 418c01445SPrabhakar Kushwaha */ 518c01445SPrabhakar Kushwaha 618c01445SPrabhakar Kushwaha #include <common.h> 724b852a7SSimon Glass #include <console.h> 818c01445SPrabhakar Kushwaha #include <malloc.h> 918c01445SPrabhakar Kushwaha #include <ns16550.h> 1018c01445SPrabhakar Kushwaha #include <nand.h> 1118c01445SPrabhakar Kushwaha #include <i2c.h> 1218c01445SPrabhakar Kushwaha #include <mmc.h> 1318c01445SPrabhakar Kushwaha #include <fsl_esdhc.h> 1418c01445SPrabhakar Kushwaha #include <spi_flash.h> 1500233528STang Yuantian #include "../common/sleep.h" 1618c01445SPrabhakar Kushwaha 1718c01445SPrabhakar Kushwaha DECLARE_GLOBAL_DATA_PTR; 1818c01445SPrabhakar Kushwaha 1918c01445SPrabhakar Kushwaha phys_size_t get_effective_memsize(void) 2018c01445SPrabhakar Kushwaha { 2118c01445SPrabhakar Kushwaha return CONFIG_SYS_L3_SIZE; 2218c01445SPrabhakar Kushwaha } 2318c01445SPrabhakar Kushwaha 2418c01445SPrabhakar Kushwaha unsigned long get_board_sys_clk(void) 2518c01445SPrabhakar Kushwaha { 2618c01445SPrabhakar Kushwaha return CONFIG_SYS_CLK_FREQ; 2718c01445SPrabhakar Kushwaha } 2818c01445SPrabhakar Kushwaha 2918c01445SPrabhakar Kushwaha unsigned long get_board_ddr_clk(void) 3018c01445SPrabhakar Kushwaha { 3118c01445SPrabhakar Kushwaha return CONFIG_DDR_CLK_FREQ; 3218c01445SPrabhakar Kushwaha } 3318c01445SPrabhakar Kushwaha 3418c01445SPrabhakar Kushwaha #define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000 3518c01445SPrabhakar Kushwaha void board_init_f(ulong bootflag) 3618c01445SPrabhakar Kushwaha { 3718c01445SPrabhakar Kushwaha u32 plat_ratio, sys_clk, uart_clk; 389f074e67SPrabhakar Kushwaha #if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND) 3918c01445SPrabhakar Kushwaha u32 porsr1, pinctl; 4031530e0bSPrabhakar Kushwaha u32 svr = get_svr(); 4118c01445SPrabhakar Kushwaha #endif 4218c01445SPrabhakar Kushwaha ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 4318c01445SPrabhakar Kushwaha 449f074e67SPrabhakar Kushwaha #if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND) 4531530e0bSPrabhakar Kushwaha if (IS_SVR_REV(svr, 1, 0)) { 4618c01445SPrabhakar Kushwaha /* 4731530e0bSPrabhakar Kushwaha * There is T1040 SoC issue where NOR, FPGA are inaccessible 4831530e0bSPrabhakar Kushwaha * during NAND boot because IFC signals > IFC_AD7 are not 4931530e0bSPrabhakar Kushwaha * enabled. This workaround changes RCW source to make all 5031530e0bSPrabhakar Kushwaha * signals enabled. 5118c01445SPrabhakar Kushwaha */ 5218c01445SPrabhakar Kushwaha porsr1 = in_be32(&gur->porsr1); 5331530e0bSPrabhakar Kushwaha pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) 5431530e0bSPrabhakar Kushwaha | 0x24800000); 5531530e0bSPrabhakar Kushwaha out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), 5631530e0bSPrabhakar Kushwaha pinctl); 5731530e0bSPrabhakar Kushwaha } 5818c01445SPrabhakar Kushwaha #endif 5918c01445SPrabhakar Kushwaha 6018c01445SPrabhakar Kushwaha /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ 6118c01445SPrabhakar Kushwaha memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); 6218c01445SPrabhakar Kushwaha 6318c01445SPrabhakar Kushwaha /* Update GD pointer */ 6418c01445SPrabhakar Kushwaha gd = (gd_t *)(CONFIG_SPL_GD_ADDR); 6518c01445SPrabhakar Kushwaha 66ce249d95STang Yuantian #ifdef CONFIG_DEEP_SLEEP 67ce249d95STang Yuantian /* disable the console if boot from deep sleep */ 6800233528STang Yuantian if (is_warm_boot()) 6900233528STang Yuantian fsl_dp_disable_console(); 70ce249d95STang Yuantian #endif 7118c01445SPrabhakar Kushwaha /* compiler optimization barrier needed for GCC >= 3.4 */ 7218c01445SPrabhakar Kushwaha __asm__ __volatile__("" : : : "memory"); 7318c01445SPrabhakar Kushwaha 7418c01445SPrabhakar Kushwaha console_init_f(); 7518c01445SPrabhakar Kushwaha 7618c01445SPrabhakar Kushwaha /* initialize selected port with appropriate baud rate */ 7718c01445SPrabhakar Kushwaha sys_clk = get_board_sys_clk(); 7818c01445SPrabhakar Kushwaha plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; 7918c01445SPrabhakar Kushwaha uart_clk = sys_clk * plat_ratio / 2; 8018c01445SPrabhakar Kushwaha 8118c01445SPrabhakar Kushwaha NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, 8218c01445SPrabhakar Kushwaha uart_clk / 16 / CONFIG_BAUDRATE); 8318c01445SPrabhakar Kushwaha 8418c01445SPrabhakar Kushwaha relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); 8518c01445SPrabhakar Kushwaha } 8618c01445SPrabhakar Kushwaha 8718c01445SPrabhakar Kushwaha void board_init_r(gd_t *gd, ulong dest_addr) 8818c01445SPrabhakar Kushwaha { 8918c01445SPrabhakar Kushwaha bd_t *bd; 9018c01445SPrabhakar Kushwaha 9118c01445SPrabhakar Kushwaha bd = (bd_t *)(gd + sizeof(gd_t)); 9218c01445SPrabhakar Kushwaha memset(bd, 0, sizeof(bd_t)); 9318c01445SPrabhakar Kushwaha gd->bd = bd; 9418c01445SPrabhakar Kushwaha bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; 9518c01445SPrabhakar Kushwaha bd->bi_memsize = CONFIG_SYS_L3_SIZE; 9618c01445SPrabhakar Kushwaha 9718c01445SPrabhakar Kushwaha probecpu(); 9818c01445SPrabhakar Kushwaha get_clocks(); 9918c01445SPrabhakar Kushwaha mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, 10018c01445SPrabhakar Kushwaha CONFIG_SPL_RELOC_MALLOC_SIZE); 101*ed4708aaSSumit Garg gd->flags |= GD_FLG_FULL_MALLOC_INIT; 10218c01445SPrabhakar Kushwaha 10318c01445SPrabhakar Kushwaha #ifdef CONFIG_SPL_MMC_BOOT 10418c01445SPrabhakar Kushwaha mmc_initialize(bd); 10518c01445SPrabhakar Kushwaha #endif 10618c01445SPrabhakar Kushwaha 10718c01445SPrabhakar Kushwaha /* relocate environment function pointers etc. */ 10818c01445SPrabhakar Kushwaha #ifdef CONFIG_SPL_NAND_BOOT 10918c01445SPrabhakar Kushwaha nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, 11018c01445SPrabhakar Kushwaha (uchar *)CONFIG_ENV_ADDR); 11118c01445SPrabhakar Kushwaha #endif 11218c01445SPrabhakar Kushwaha #ifdef CONFIG_SPL_MMC_BOOT 11318c01445SPrabhakar Kushwaha mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, 11418c01445SPrabhakar Kushwaha (uchar *)CONFIG_ENV_ADDR); 11518c01445SPrabhakar Kushwaha #endif 11618c01445SPrabhakar Kushwaha #ifdef CONFIG_SPL_SPI_BOOT 11718c01445SPrabhakar Kushwaha spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, 11818c01445SPrabhakar Kushwaha (uchar *)CONFIG_ENV_ADDR); 11918c01445SPrabhakar Kushwaha #endif 12018c01445SPrabhakar Kushwaha gd->env_addr = (ulong)(CONFIG_ENV_ADDR); 12118c01445SPrabhakar Kushwaha gd->env_valid = 1; 12218c01445SPrabhakar Kushwaha 12318c01445SPrabhakar Kushwaha i2c_init_all(); 12418c01445SPrabhakar Kushwaha 12518c01445SPrabhakar Kushwaha puts("\n\n"); 12618c01445SPrabhakar Kushwaha 12718c01445SPrabhakar Kushwaha gd->ram_size = initdram(0); 12818c01445SPrabhakar Kushwaha 12918c01445SPrabhakar Kushwaha #ifdef CONFIG_SPL_MMC_BOOT 13018c01445SPrabhakar Kushwaha mmc_boot(); 13118c01445SPrabhakar Kushwaha #elif defined(CONFIG_SPL_SPI_BOOT) 13218c01445SPrabhakar Kushwaha spi_boot(); 13318c01445SPrabhakar Kushwaha #elif defined(CONFIG_SPL_NAND_BOOT) 13418c01445SPrabhakar Kushwaha nand_boot(); 13518c01445SPrabhakar Kushwaha #endif 13618c01445SPrabhakar Kushwaha } 137