1*18c01445SPrabhakar Kushwaha /* Copyright 2013 Freescale Semiconductor, Inc. 2*18c01445SPrabhakar Kushwaha * 3*18c01445SPrabhakar Kushwaha * SPDX-License-Identifier: GPL-2.0+ 4*18c01445SPrabhakar Kushwaha */ 5*18c01445SPrabhakar Kushwaha 6*18c01445SPrabhakar Kushwaha #include <common.h> 7*18c01445SPrabhakar Kushwaha #include <malloc.h> 8*18c01445SPrabhakar Kushwaha #include <ns16550.h> 9*18c01445SPrabhakar Kushwaha #include <nand.h> 10*18c01445SPrabhakar Kushwaha #include <i2c.h> 11*18c01445SPrabhakar Kushwaha #include <mmc.h> 12*18c01445SPrabhakar Kushwaha #include <fsl_esdhc.h> 13*18c01445SPrabhakar Kushwaha #include <spi_flash.h> 14*18c01445SPrabhakar Kushwaha 15*18c01445SPrabhakar Kushwaha DECLARE_GLOBAL_DATA_PTR; 16*18c01445SPrabhakar Kushwaha 17*18c01445SPrabhakar Kushwaha phys_size_t get_effective_memsize(void) 18*18c01445SPrabhakar Kushwaha { 19*18c01445SPrabhakar Kushwaha return CONFIG_SYS_L3_SIZE; 20*18c01445SPrabhakar Kushwaha } 21*18c01445SPrabhakar Kushwaha 22*18c01445SPrabhakar Kushwaha unsigned long get_board_sys_clk(void) 23*18c01445SPrabhakar Kushwaha { 24*18c01445SPrabhakar Kushwaha return CONFIG_SYS_CLK_FREQ; 25*18c01445SPrabhakar Kushwaha } 26*18c01445SPrabhakar Kushwaha 27*18c01445SPrabhakar Kushwaha unsigned long get_board_ddr_clk(void) 28*18c01445SPrabhakar Kushwaha { 29*18c01445SPrabhakar Kushwaha return CONFIG_DDR_CLK_FREQ; 30*18c01445SPrabhakar Kushwaha } 31*18c01445SPrabhakar Kushwaha 32*18c01445SPrabhakar Kushwaha #define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000 33*18c01445SPrabhakar Kushwaha void board_init_f(ulong bootflag) 34*18c01445SPrabhakar Kushwaha { 35*18c01445SPrabhakar Kushwaha u32 plat_ratio, sys_clk, uart_clk; 36*18c01445SPrabhakar Kushwaha #ifdef CONFIG_SPL_NAND_BOOT 37*18c01445SPrabhakar Kushwaha u32 porsr1, pinctl; 38*18c01445SPrabhakar Kushwaha #endif 39*18c01445SPrabhakar Kushwaha ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 40*18c01445SPrabhakar Kushwaha 41*18c01445SPrabhakar Kushwaha #ifdef CONFIG_SPL_NAND_BOOT 42*18c01445SPrabhakar Kushwaha /* 43*18c01445SPrabhakar Kushwaha * There is T1040 SoC issue where NOR, FPGA are inaccessible during 44*18c01445SPrabhakar Kushwaha * NAND boot because IFC signals > IFC_AD7 are not enabled. 45*18c01445SPrabhakar Kushwaha * This workaround changes RCW source to make all signals enabled. 46*18c01445SPrabhakar Kushwaha */ 47*18c01445SPrabhakar Kushwaha porsr1 = in_be32(&gur->porsr1); 48*18c01445SPrabhakar Kushwaha pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000); 49*18c01445SPrabhakar Kushwaha out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl); 50*18c01445SPrabhakar Kushwaha #endif 51*18c01445SPrabhakar Kushwaha 52*18c01445SPrabhakar Kushwaha /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ 53*18c01445SPrabhakar Kushwaha memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); 54*18c01445SPrabhakar Kushwaha 55*18c01445SPrabhakar Kushwaha /* Update GD pointer */ 56*18c01445SPrabhakar Kushwaha gd = (gd_t *)(CONFIG_SPL_GD_ADDR); 57*18c01445SPrabhakar Kushwaha 58*18c01445SPrabhakar Kushwaha /* compiler optimization barrier needed for GCC >= 3.4 */ 59*18c01445SPrabhakar Kushwaha __asm__ __volatile__("" : : : "memory"); 60*18c01445SPrabhakar Kushwaha 61*18c01445SPrabhakar Kushwaha console_init_f(); 62*18c01445SPrabhakar Kushwaha 63*18c01445SPrabhakar Kushwaha /* initialize selected port with appropriate baud rate */ 64*18c01445SPrabhakar Kushwaha sys_clk = get_board_sys_clk(); 65*18c01445SPrabhakar Kushwaha plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; 66*18c01445SPrabhakar Kushwaha uart_clk = sys_clk * plat_ratio / 2; 67*18c01445SPrabhakar Kushwaha 68*18c01445SPrabhakar Kushwaha NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, 69*18c01445SPrabhakar Kushwaha uart_clk / 16 / CONFIG_BAUDRATE); 70*18c01445SPrabhakar Kushwaha 71*18c01445SPrabhakar Kushwaha relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); 72*18c01445SPrabhakar Kushwaha } 73*18c01445SPrabhakar Kushwaha 74*18c01445SPrabhakar Kushwaha void board_init_r(gd_t *gd, ulong dest_addr) 75*18c01445SPrabhakar Kushwaha { 76*18c01445SPrabhakar Kushwaha bd_t *bd; 77*18c01445SPrabhakar Kushwaha 78*18c01445SPrabhakar Kushwaha bd = (bd_t *)(gd + sizeof(gd_t)); 79*18c01445SPrabhakar Kushwaha memset(bd, 0, sizeof(bd_t)); 80*18c01445SPrabhakar Kushwaha gd->bd = bd; 81*18c01445SPrabhakar Kushwaha bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; 82*18c01445SPrabhakar Kushwaha bd->bi_memsize = CONFIG_SYS_L3_SIZE; 83*18c01445SPrabhakar Kushwaha 84*18c01445SPrabhakar Kushwaha probecpu(); 85*18c01445SPrabhakar Kushwaha get_clocks(); 86*18c01445SPrabhakar Kushwaha mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, 87*18c01445SPrabhakar Kushwaha CONFIG_SPL_RELOC_MALLOC_SIZE); 88*18c01445SPrabhakar Kushwaha 89*18c01445SPrabhakar Kushwaha #ifdef CONFIG_SPL_MMC_BOOT 90*18c01445SPrabhakar Kushwaha mmc_initialize(bd); 91*18c01445SPrabhakar Kushwaha #endif 92*18c01445SPrabhakar Kushwaha 93*18c01445SPrabhakar Kushwaha /* relocate environment function pointers etc. */ 94*18c01445SPrabhakar Kushwaha #ifdef CONFIG_SPL_NAND_BOOT 95*18c01445SPrabhakar Kushwaha nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, 96*18c01445SPrabhakar Kushwaha (uchar *)CONFIG_ENV_ADDR); 97*18c01445SPrabhakar Kushwaha #endif 98*18c01445SPrabhakar Kushwaha #ifdef CONFIG_SPL_MMC_BOOT 99*18c01445SPrabhakar Kushwaha mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, 100*18c01445SPrabhakar Kushwaha (uchar *)CONFIG_ENV_ADDR); 101*18c01445SPrabhakar Kushwaha #endif 102*18c01445SPrabhakar Kushwaha #ifdef CONFIG_SPL_SPI_BOOT 103*18c01445SPrabhakar Kushwaha spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, 104*18c01445SPrabhakar Kushwaha (uchar *)CONFIG_ENV_ADDR); 105*18c01445SPrabhakar Kushwaha #endif 106*18c01445SPrabhakar Kushwaha gd->env_addr = (ulong)(CONFIG_ENV_ADDR); 107*18c01445SPrabhakar Kushwaha gd->env_valid = 1; 108*18c01445SPrabhakar Kushwaha 109*18c01445SPrabhakar Kushwaha i2c_init_all(); 110*18c01445SPrabhakar Kushwaha 111*18c01445SPrabhakar Kushwaha puts("\n\n"); 112*18c01445SPrabhakar Kushwaha 113*18c01445SPrabhakar Kushwaha gd->ram_size = initdram(0); 114*18c01445SPrabhakar Kushwaha 115*18c01445SPrabhakar Kushwaha #ifdef CONFIG_SPL_MMC_BOOT 116*18c01445SPrabhakar Kushwaha mmc_boot(); 117*18c01445SPrabhakar Kushwaha #elif defined(CONFIG_SPL_SPI_BOOT) 118*18c01445SPrabhakar Kushwaha spi_boot(); 119*18c01445SPrabhakar Kushwaha #elif defined(CONFIG_SPL_NAND_BOOT) 120*18c01445SPrabhakar Kushwaha nand_boot(); 121*18c01445SPrabhakar Kushwaha #endif 122*18c01445SPrabhakar Kushwaha } 123