1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __DDR_H__ 8 #define __DDR_H__ 9 10 dimm_params_t ddr_raw_timing = { 11 .n_ranks = 2, 12 .rank_density = 2147483648u, 13 .capacity = 4294967296u, 14 .primary_sdram_width = 64, 15 .ec_sdram_width = 8, 16 .registered_dimm = 0, 17 .mirrored_dimm = 1, 18 .n_row_addr = 15, 19 .n_col_addr = 10, 20 .n_banks_per_sdram_device = 8, 21 .edc_config = 2, /* ECC */ 22 .burst_lengths_bitmask = 0x0c, 23 24 .tckmin_x_ps = 1071, 25 .caslat_x = 0x2fe << 4, /* 5,6,7,8,9,10,11,13 */ 26 .taa_ps = 13910, 27 .twr_ps = 15000, 28 .trcd_ps = 13910, 29 .trrd_ps = 6000, 30 .trp_ps = 13910, 31 .tras_ps = 34000, 32 .trc_ps = 48910, 33 .trfc_ps = 260000, 34 .twtr_ps = 7500, 35 .trtp_ps = 7500, 36 .refresh_rate_ps = 7800000, 37 .tfaw_ps = 35000, 38 }; 39 40 struct board_specific_parameters { 41 u32 n_ranks; 42 u32 datarate_mhz_high; 43 u32 rank_gb; 44 u32 clk_adjust; 45 u32 wrlvl_start; 46 u32 wrlvl_ctl_2; 47 u32 wrlvl_ctl_3; 48 u32 cpo; 49 u32 write_data_delay; 50 u32 force_2t; 51 }; 52 53 /* 54 * These tables contain all valid speeds we want to override with board 55 * specific parameters. datarate_mhz_high values need to be in ascending order 56 * for each n_ranks group. 57 */ 58 59 static const struct board_specific_parameters udimm0[] = { 60 /* 61 * memory controller 0 62 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T 63 * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | 64 */ 65 {2, 1066, 4, 8, 4, 0x05070609, 0x08090a08, 0xff, 2, 0}, 66 {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, 67 {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0}, 68 {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0}, 69 {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0}, 70 {} 71 }; 72 73 static const struct board_specific_parameters *udimms[] = { 74 udimm0, 75 }; 76 #endif 77