1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <i2c.h> 9 #include <hwconfig.h> 10 #include <asm/mmu.h> 11 #include <fsl_ddr_sdram.h> 12 #include <fsl_ddr_dimm_params.h> 13 #include <asm/fsl_law.h> 14 #include "ddr.h" 15 16 DECLARE_GLOBAL_DATA_PTR; 17 18 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, 19 unsigned int controller_number, 20 unsigned int dimm_number) 21 { 22 const char dimm_model[] = "RAW timing DDR"; 23 24 if ((controller_number == 0) && (dimm_number == 0)) { 25 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); 26 memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); 27 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); 28 } 29 30 return 0; 31 } 32 33 void fsl_ddr_board_options(memctl_options_t *popts, 34 dimm_params_t *pdimm, 35 unsigned int ctrl_num) 36 { 37 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; 38 ulong ddr_freq; 39 40 if (ctrl_num > 1) { 41 printf("Not supported controller number %d\n", ctrl_num); 42 return; 43 } 44 if (!pdimm->n_ranks) 45 return; 46 47 pbsp = udimms[0]; 48 49 /* Get clk_adjust according to the board ddr 50 * freqency and n_banks specified in board_specific_parameters table. 51 */ 52 ddr_freq = get_ddr_freq(0) / 1000000; 53 while (pbsp->datarate_mhz_high) { 54 if (pbsp->n_ranks == pdimm->n_ranks && 55 (pdimm->rank_density >> 30) >= pbsp->rank_gb) { 56 if (ddr_freq <= pbsp->datarate_mhz_high) { 57 popts->clk_adjust = pbsp->clk_adjust; 58 popts->wrlvl_start = pbsp->wrlvl_start; 59 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; 60 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; 61 goto found; 62 } 63 pbsp_highest = pbsp; 64 } 65 pbsp++; 66 } 67 68 if (pbsp_highest) { 69 printf("Error: board specific timing not found\n"); 70 printf("for data rate %lu MT/s\n", ddr_freq); 71 printf("Trying to use the highest speed (%u) parameters\n", 72 pbsp_highest->datarate_mhz_high); 73 popts->clk_adjust = pbsp_highest->clk_adjust; 74 popts->wrlvl_start = pbsp_highest->wrlvl_start; 75 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; 76 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; 77 } else { 78 panic("DIMM is not supported by this board"); 79 } 80 found: 81 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" 82 "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, " 83 "wrlvl_ctrl_3 0x%x\n", 84 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, 85 pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, 86 pbsp->wrlvl_ctl_3); 87 88 /* 89 * Factors to consider for half-strength driver enable: 90 * - number of DIMMs installed 91 */ 92 popts->half_strength_driver_enable = 0; 93 /* 94 * Write leveling override 95 */ 96 popts->wrlvl_override = 1; 97 popts->wrlvl_sample = 0xf; 98 99 /* 100 * rtt and rtt_wr override 101 */ 102 popts->rtt_override = 0; 103 104 /* Enable ZQ calibration */ 105 popts->zq_en = 1; 106 107 /* DHC_EN =1, ODT = 75 Ohm */ 108 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_OFF); 109 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_OFF); 110 } 111 112 phys_size_t initdram(int board_type) 113 { 114 phys_size_t dram_size; 115 116 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) 117 puts("Initializing....using SPD\n"); 118 119 dram_size = fsl_ddr_sdram(); 120 121 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 122 dram_size *= 0x100000; 123 124 #else 125 dram_size = fsl_ddr_sdram_size(); 126 #endif 127 return dram_size; 128 } 129