1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <i2c.h> 9 #include <hwconfig.h> 10 #include <asm/mmu.h> 11 #include <fsl_ddr_sdram.h> 12 #include <fsl_ddr_dimm_params.h> 13 #include <asm/fsl_law.h> 14 #include <asm/mpc85xx_gpio.h> 15 #include "ddr.h" 16 17 DECLARE_GLOBAL_DATA_PTR; 18 19 void fsl_ddr_board_options(memctl_options_t *popts, 20 dimm_params_t *pdimm, 21 unsigned int ctrl_num) 22 { 23 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; 24 ulong ddr_freq; 25 26 if (ctrl_num > 1) { 27 printf("Not supported controller number %d\n", ctrl_num); 28 return; 29 } 30 if (!pdimm->n_ranks) 31 return; 32 33 pbsp = udimms[0]; 34 35 /* Get clk_adjust according to the board ddr 36 * freqency and n_banks specified in board_specific_parameters table. 37 */ 38 ddr_freq = get_ddr_freq(0) / 1000000; 39 while (pbsp->datarate_mhz_high) { 40 if (pbsp->n_ranks == pdimm->n_ranks && 41 (pdimm->rank_density >> 30) >= pbsp->rank_gb) { 42 if (ddr_freq <= pbsp->datarate_mhz_high) { 43 popts->clk_adjust = pbsp->clk_adjust; 44 popts->wrlvl_start = pbsp->wrlvl_start; 45 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; 46 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; 47 goto found; 48 } 49 pbsp_highest = pbsp; 50 } 51 pbsp++; 52 } 53 54 if (pbsp_highest) { 55 printf("Error: board specific timing not found\n"); 56 printf("for data rate %lu MT/s\n", ddr_freq); 57 printf("Trying to use the highest speed (%u) parameters\n", 58 pbsp_highest->datarate_mhz_high); 59 popts->clk_adjust = pbsp_highest->clk_adjust; 60 popts->wrlvl_start = pbsp_highest->wrlvl_start; 61 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; 62 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; 63 } else { 64 panic("DIMM is not supported by this board"); 65 } 66 found: 67 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" 68 "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, " 69 "wrlvl_ctrl_3 0x%x\n", 70 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, 71 pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, 72 pbsp->wrlvl_ctl_3); 73 74 /* 75 * Factors to consider for half-strength driver enable: 76 * - number of DIMMs installed 77 */ 78 #ifdef CONFIG_SYS_FSL_DDR4 79 popts->half_strength_driver_enable = 1; 80 #else 81 popts->half_strength_driver_enable = 0; 82 #endif 83 /* 84 * Write leveling override 85 */ 86 popts->wrlvl_override = 1; 87 popts->wrlvl_sample = 0xf; 88 89 /* 90 * rtt and rtt_wr override 91 */ 92 popts->rtt_override = 0; 93 94 /* Enable ZQ calibration */ 95 popts->zq_en = 1; 96 97 /* DHC_EN =1, ODT = 75 Ohm */ 98 #ifdef CONFIG_SYS_FSL_DDR4 99 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_120OHM); 100 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_120OHM) | 101 DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ 102 #else 103 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); 104 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); 105 #endif 106 } 107 108 #if defined(CONFIG_DEEP_SLEEP) 109 void board_mem_sleep_setup(void) 110 { 111 void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE; 112 113 /* does not provide HW signals for power management */ 114 clrbits_8(cpld_base + 0x17, 0x40); 115 /* Disable MCKE isolation */ 116 gpio_set_value(2, 0); 117 udelay(1); 118 } 119 #endif 120 121 phys_size_t initdram(int board_type) 122 { 123 phys_size_t dram_size; 124 125 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) 126 puts("Initializing....using SPD\n"); 127 128 dram_size = fsl_ddr_sdram(); 129 130 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 131 dram_size *= 0x100000; 132 133 #else 134 dram_size = fsl_ddr_sdram_size(); 135 #endif 136 137 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) 138 fsl_dp_resume(); 139 #endif 140 141 return dram_size; 142 } 143