1 /*
2  * Copyright 2013 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <command.h>
9 #include <i2c.h>
10 #include <netdev.h>
11 #include <linux/compiler.h>
12 #include <asm/mmu.h>
13 #include <asm/processor.h>
14 #include <asm/cache.h>
15 #include <asm/immap_85xx.h>
16 #include <asm/fsl_law.h>
17 #include <asm/fsl_serdes.h>
18 #include <asm/fsl_liodn.h>
19 #include <fm_eth.h>
20 #include <hwconfig.h>
21 
22 #include "../common/sleep.h"
23 #include "../common/qixis.h"
24 #include "t1040qds.h"
25 #include "t1040qds_qixis.h"
26 
27 DECLARE_GLOBAL_DATA_PTR;
28 
29 int checkboard(void)
30 {
31 	char buf[64];
32 	u8 sw;
33 	struct cpu_type *cpu = gd->arch.cpu;
34 	static const char *const freq[] = {"100", "125", "156.25", "161.13",
35 						"122.88", "122.88", "122.88"};
36 	int clock;
37 
38 	printf("Board: %sQDS, ", cpu->name);
39 	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
40 	       QIXIS_READ(id), QIXIS_READ(arch));
41 
42 	sw = QIXIS_READ(brdcfg[0]);
43 	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
44 
45 	if (sw < 0x8)
46 		printf("vBank: %d\n", sw);
47 	else if (sw == 0x8)
48 		puts("PromJet\n");
49 	else if (sw == 0x9)
50 		puts("NAND\n");
51 	else if (sw == 0x15)
52 		printf("IFCCard\n");
53 	else
54 		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
55 
56 	printf("FPGA: v%d (%s), build %d",
57 	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
58 	       (int)qixis_read_minor());
59 	/* the timestamp string contains "\n" at the end */
60 	printf(" on %s", qixis_read_time(buf));
61 
62 	/*
63 	 * Display the actual SERDES reference clocks as configured by the
64 	 * dip switches on the board.  Note that the SWx registers could
65 	 * technically be set to force the reference clocks to match the
66 	 * values that the SERDES expects (or vice versa).  For now, however,
67 	 * we just display both values and hope the user notices when they
68 	 * don't match.
69 	 */
70 	puts("SERDES Reference: ");
71 	sw = QIXIS_READ(brdcfg[2]);
72 	clock = (sw >> 6) & 3;
73 	printf("Clock1=%sMHz ", freq[clock]);
74 	clock = (sw >> 4) & 3;
75 	printf("Clock2=%sMHz\n", freq[clock]);
76 
77 	return 0;
78 }
79 
80 int select_i2c_ch_pca9547(u8 ch)
81 {
82 	int ret;
83 
84 	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
85 	if (ret) {
86 		puts("PCA: failed to select proper channel\n");
87 		return ret;
88 	}
89 
90 	return 0;
91 }
92 
93 static void qe_board_setup(void)
94 {
95 	u8 brdcfg15, brdcfg9;
96 
97 	if (hwconfig("qe") && hwconfig("tdm")) {
98 		brdcfg15 = QIXIS_READ(brdcfg[15]);
99 		/*
100 		 * TDMRiser uses QE-TDM
101 		 * Route QE_TDM signals to TDM Riser slot
102 		 */
103 		QIXIS_WRITE(brdcfg[15], brdcfg15 | 7);
104 	} else if (hwconfig("qe") && hwconfig("uart")) {
105 		brdcfg15 = QIXIS_READ(brdcfg[15]);
106 		brdcfg9 = QIXIS_READ(brdcfg[9]);
107 		/*
108 		 * Route QE_TDM signals to UCC
109 		 * ProfiBus controlled by UCC3
110 		 */
111 		brdcfg15 &= 0xfc;
112 		QIXIS_WRITE(brdcfg[15], brdcfg15 | 2);
113 		QIXIS_WRITE(brdcfg[9], brdcfg9 | 4);
114 	}
115 }
116 
117 int board_early_init_f(void)
118 {
119 #if defined(CONFIG_DEEP_SLEEP)
120 	if (is_warm_boot())
121 		fsl_dp_disable_console();
122 #endif
123 
124 	return 0;
125 }
126 
127 int board_early_init_r(void)
128 {
129 #ifdef CONFIG_SYS_FLASH_BASE
130 	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
131 	int flash_esel = find_tlb_idx((void *)flashbase, 1);
132 
133 	/*
134 	 * Remap Boot flash + PROMJET region to caching-inhibited
135 	 * so that flash can be erased properly.
136 	 */
137 
138 	/* Flush d-cache and invalidate i-cache of any FLASH data */
139 	flush_dcache();
140 	invalidate_icache();
141 
142 	if (flash_esel == -1) {
143 		/* very unlikely unless something is messed up */
144 		puts("Error: Could not find TLB for FLASH BASE\n");
145 		flash_esel = 2;	/* give our best effort to continue */
146 	} else {
147 		/* invalidate existing TLB entry for flash + promjet */
148 		disable_tlb(flash_esel);
149 	}
150 
151 	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
152 		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
153 		0, flash_esel, BOOKE_PAGESZ_256M, 1);
154 #endif
155 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
156 
157 	return 0;
158 }
159 
160 unsigned long get_board_sys_clk(void)
161 {
162 	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
163 
164 	switch (sysclk_conf & 0x0F) {
165 	case QIXIS_SYSCLK_64:
166 		return 64000000;
167 	case QIXIS_SYSCLK_83:
168 		return 83333333;
169 	case QIXIS_SYSCLK_100:
170 		return 100000000;
171 	case QIXIS_SYSCLK_125:
172 		return 125000000;
173 	case QIXIS_SYSCLK_133:
174 		return 133333333;
175 	case QIXIS_SYSCLK_150:
176 		return 150000000;
177 	case QIXIS_SYSCLK_160:
178 		return 160000000;
179 	case QIXIS_SYSCLK_166:
180 		return 166666666;
181 	}
182 	return 66666666;
183 }
184 
185 unsigned long get_board_ddr_clk(void)
186 {
187 	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
188 
189 	switch ((ddrclk_conf & 0x30) >> 4) {
190 	case QIXIS_DDRCLK_100:
191 		return 100000000;
192 	case QIXIS_DDRCLK_125:
193 		return 125000000;
194 	case QIXIS_DDRCLK_133:
195 		return 133333333;
196 	}
197 	return 66666666;
198 }
199 
200 #define NUM_SRDS_BANKS	2
201 int misc_init_r(void)
202 {
203 	u8 sw;
204 	serdes_corenet_t *srds_regs =
205 		(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
206 	u32 actual[NUM_SRDS_BANKS] = { 0 };
207 	int i;
208 
209 	sw = QIXIS_READ(brdcfg[2]);
210 	for (i = 0; i < NUM_SRDS_BANKS; i++) {
211 		unsigned int clock = (sw >> (6 - 2 * i)) & 3;
212 		switch (clock) {
213 		case 0:
214 			actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
215 			break;
216 		case 1:
217 			actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
218 			break;
219 		case 2:
220 			actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
221 			break;
222 		}
223 	}
224 
225 	puts("SerDes1");
226 	for (i = 0; i < NUM_SRDS_BANKS; i++) {
227 		u32 pllcr0 = srds_regs->bank[i].pllcr0;
228 		u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
229 		if (expected != actual[i]) {
230 			printf("expects ref clk%d %sMHz, but actual is %sMHz\n",
231 			       i + 1, serdes_clock_to_string(expected),
232 			       serdes_clock_to_string(actual[i]));
233 		}
234 	}
235 
236 	qe_board_setup();
237 
238 	return 0;
239 }
240 
241 int ft_board_setup(void *blob, bd_t *bd)
242 {
243 	phys_addr_t base;
244 	phys_size_t size;
245 
246 	ft_cpu_setup(blob, bd);
247 
248 	base = getenv_bootm_low();
249 	size = getenv_bootm_size();
250 
251 	fdt_fixup_memory(blob, (u64)base, (u64)size);
252 
253 #ifdef CONFIG_PCI
254 	pci_of_setup(blob, bd);
255 #endif
256 
257 	fdt_fixup_liodn(blob);
258 
259 #ifdef CONFIG_HAS_FSL_DR_USB
260 	fdt_fixup_dr_usb(blob, bd);
261 #endif
262 
263 #ifdef CONFIG_SYS_DPAA_FMAN
264 	fdt_fixup_fman_ethernet(blob);
265 	fdt_fixup_board_enet(blob);
266 #endif
267 
268 	return 0;
269 }
270 
271 void qixis_dump_switch(void)
272 {
273 	int i, nr_of_cfgsw;
274 
275 	QIXIS_WRITE(cms[0], 0x00);
276 	nr_of_cfgsw = QIXIS_READ(cms[1]);
277 
278 	puts("DIP switch settings dump:\n");
279 	for (i = 1; i <= nr_of_cfgsw; i++) {
280 		QIXIS_WRITE(cms[0], i);
281 		printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
282 	}
283 }
284 
285 int board_need_mem_reset(void)
286 {
287 	return 1;
288 }
289