1 /*
2  * Copyright 2013 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <command.h>
9 #include <i2c.h>
10 #include <netdev.h>
11 #include <linux/compiler.h>
12 #include <asm/mmu.h>
13 #include <asm/processor.h>
14 #include <asm/cache.h>
15 #include <asm/immap_85xx.h>
16 #include <asm/fsl_law.h>
17 #include <asm/fsl_serdes.h>
18 #include <asm/fsl_portals.h>
19 #include <asm/fsl_liodn.h>
20 #include <fm_eth.h>
21 #include <hwconfig.h>
22 #include <asm/mpc85xx_gpio.h>
23 
24 #include "../common/qixis.h"
25 #include "t1040qds.h"
26 #include "t1040qds_qixis.h"
27 
28 DECLARE_GLOBAL_DATA_PTR;
29 
30 int checkboard(void)
31 {
32 	char buf[64];
33 	u8 sw;
34 	struct cpu_type *cpu = gd->arch.cpu;
35 	static const char *const freq[] = {"100", "125", "156.25", "161.13",
36 						"122.88", "122.88", "122.88"};
37 	int clock;
38 
39 	printf("Board: %sQDS, ", cpu->name);
40 	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
41 	       QIXIS_READ(id), QIXIS_READ(arch));
42 
43 	sw = QIXIS_READ(brdcfg[0]);
44 	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
45 
46 	if (sw < 0x8)
47 		printf("vBank: %d\n", sw);
48 	else if (sw == 0x8)
49 		puts("PromJet\n");
50 	else if (sw == 0x9)
51 		puts("NAND\n");
52 	else if (sw == 0x15)
53 		printf("IFCCard\n");
54 	else
55 		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
56 
57 	printf("FPGA: v%d (%s), build %d",
58 	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
59 	       (int)qixis_read_minor());
60 	/* the timestamp string contains "\n" at the end */
61 	printf(" on %s", qixis_read_time(buf));
62 
63 	/*
64 	 * Display the actual SERDES reference clocks as configured by the
65 	 * dip switches on the board.  Note that the SWx registers could
66 	 * technically be set to force the reference clocks to match the
67 	 * values that the SERDES expects (or vice versa).  For now, however,
68 	 * we just display both values and hope the user notices when they
69 	 * don't match.
70 	 */
71 	puts("SERDES Reference: ");
72 	sw = QIXIS_READ(brdcfg[2]);
73 	clock = (sw >> 6) & 3;
74 	printf("Clock1=%sMHz ", freq[clock]);
75 	clock = (sw >> 4) & 3;
76 	printf("Clock2=%sMHz\n", freq[clock]);
77 
78 	return 0;
79 }
80 
81 int select_i2c_ch_pca9547(u8 ch)
82 {
83 	int ret;
84 
85 	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
86 	if (ret) {
87 		puts("PCA: failed to select proper channel\n");
88 		return ret;
89 	}
90 
91 	return 0;
92 }
93 
94 static void qe_board_setup(void)
95 {
96 	u8 brdcfg15, brdcfg9;
97 
98 	if (hwconfig("qe") && hwconfig("tdm")) {
99 		brdcfg15 = QIXIS_READ(brdcfg[15]);
100 		/*
101 		 * TDMRiser uses QE-TDM
102 		 * Route QE_TDM signals to TDM Riser slot
103 		 */
104 		QIXIS_WRITE(brdcfg[15], brdcfg15 | 7);
105 	} else if (hwconfig("qe") && hwconfig("uart")) {
106 		brdcfg15 = QIXIS_READ(brdcfg[15]);
107 		brdcfg9 = QIXIS_READ(brdcfg[9]);
108 		/*
109 		 * Route QE_TDM signals to UCC
110 		 * ProfiBus controlled by UCC3
111 		 */
112 		brdcfg15 &= 0xfc;
113 		QIXIS_WRITE(brdcfg[15], brdcfg15 | 2);
114 		QIXIS_WRITE(brdcfg[9], brdcfg9 | 4);
115 	}
116 }
117 
118 int board_early_init_r(void)
119 {
120 #ifdef CONFIG_SYS_FLASH_BASE
121 	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
122 	int flash_esel = find_tlb_idx((void *)flashbase, 1);
123 
124 	/*
125 	 * Remap Boot flash + PROMJET region to caching-inhibited
126 	 * so that flash can be erased properly.
127 	 */
128 
129 	/* Flush d-cache and invalidate i-cache of any FLASH data */
130 	flush_dcache();
131 	invalidate_icache();
132 
133 	if (flash_esel == -1) {
134 		/* very unlikely unless something is messed up */
135 		puts("Error: Could not find TLB for FLASH BASE\n");
136 		flash_esel = 2;	/* give our best effort to continue */
137 	} else {
138 		/* invalidate existing TLB entry for flash + promjet */
139 		disable_tlb(flash_esel);
140 	}
141 
142 	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
143 		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
144 		0, flash_esel, BOOKE_PAGESZ_256M, 1);
145 #endif
146 	set_liodns();
147 #ifdef CONFIG_SYS_DPAA_QBMAN
148 	setup_portals();
149 #endif
150 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
151 
152 	return 0;
153 }
154 
155 unsigned long get_board_sys_clk(void)
156 {
157 	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
158 
159 	switch (sysclk_conf & 0x0F) {
160 	case QIXIS_SYSCLK_64:
161 		return 64000000;
162 	case QIXIS_SYSCLK_83:
163 		return 83333333;
164 	case QIXIS_SYSCLK_100:
165 		return 100000000;
166 	case QIXIS_SYSCLK_125:
167 		return 125000000;
168 	case QIXIS_SYSCLK_133:
169 		return 133333333;
170 	case QIXIS_SYSCLK_150:
171 		return 150000000;
172 	case QIXIS_SYSCLK_160:
173 		return 160000000;
174 	case QIXIS_SYSCLK_166:
175 		return 166666666;
176 	}
177 	return 66666666;
178 }
179 
180 unsigned long get_board_ddr_clk(void)
181 {
182 	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
183 
184 	switch ((ddrclk_conf & 0x30) >> 4) {
185 	case QIXIS_DDRCLK_100:
186 		return 100000000;
187 	case QIXIS_DDRCLK_125:
188 		return 125000000;
189 	case QIXIS_DDRCLK_133:
190 		return 133333333;
191 	}
192 	return 66666666;
193 }
194 
195 #define NUM_SRDS_BANKS	2
196 int misc_init_r(void)
197 {
198 	u8 sw;
199 	serdes_corenet_t *srds_regs =
200 		(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
201 	u32 actual[NUM_SRDS_BANKS] = { 0 };
202 	int i;
203 
204 	sw = QIXIS_READ(brdcfg[2]);
205 	for (i = 0; i < NUM_SRDS_BANKS; i++) {
206 		unsigned int clock = (sw >> (6 - 2 * i)) & 3;
207 		switch (clock) {
208 		case 0:
209 			actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
210 			break;
211 		case 1:
212 			actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
213 			break;
214 		case 2:
215 			actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
216 			break;
217 		}
218 	}
219 
220 	puts("SerDes1");
221 	for (i = 0; i < NUM_SRDS_BANKS; i++) {
222 		u32 pllcr0 = srds_regs->bank[i].pllcr0;
223 		u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
224 		if (expected != actual[i]) {
225 			printf("expects ref clk%d %sMHz, but actual is %sMHz\n",
226 			       i + 1, serdes_clock_to_string(expected),
227 			       serdes_clock_to_string(actual[i]));
228 		}
229 	}
230 
231 	qe_board_setup();
232 
233 	return 0;
234 }
235 
236 void ft_board_setup(void *blob, bd_t *bd)
237 {
238 	phys_addr_t base;
239 	phys_size_t size;
240 
241 	ft_cpu_setup(blob, bd);
242 
243 	base = getenv_bootm_low();
244 	size = getenv_bootm_size();
245 
246 	fdt_fixup_memory(blob, (u64)base, (u64)size);
247 
248 #ifdef CONFIG_PCI
249 	pci_of_setup(blob, bd);
250 #endif
251 
252 	fdt_fixup_liodn(blob);
253 
254 #ifdef CONFIG_HAS_FSL_DR_USB
255 	fdt_fixup_dr_usb(blob, bd);
256 #endif
257 
258 #ifdef CONFIG_SYS_DPAA_FMAN
259 	fdt_fixup_fman_ethernet(blob);
260 	fdt_fixup_board_enet(blob);
261 #endif
262 }
263 
264 void qixis_dump_switch(void)
265 {
266 	int i, nr_of_cfgsw;
267 
268 	QIXIS_WRITE(cms[0], 0x00);
269 	nr_of_cfgsw = QIXIS_READ(cms[1]);
270 
271 	puts("DIP switch settings dump:\n");
272 	for (i = 1; i <= nr_of_cfgsw; i++) {
273 		QIXIS_WRITE(cms[0], i);
274 		printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
275 	}
276 }
277 
278 int board_need_mem_reset(void)
279 {
280 	return 1;
281 }
282 
283 #ifdef CONFIG_DEEP_SLEEP
284 void board_mem_sleep_setup(void)
285 {
286 	/* does not provide HW signals for power management */
287 	QIXIS_WRITE(pwr_ctl[1], (QIXIS_READ(pwr_ctl[1]) & ~0x2));
288 	/* Disable MCKE isolation */
289 	gpio_set_value(2, 0);
290 	udelay(1);
291 }
292 #endif
293