17d436078SPrabhakar Kushwaha /* 27d436078SPrabhakar Kushwaha * Copyright 2013 Freescale Semiconductor, Inc. 37d436078SPrabhakar Kushwaha * 47d436078SPrabhakar Kushwaha * SPDX-License-Identifier: GPL-2.0+ 57d436078SPrabhakar Kushwaha */ 67d436078SPrabhakar Kushwaha 77d436078SPrabhakar Kushwaha #include <common.h> 87d436078SPrabhakar Kushwaha #include <command.h> 97d436078SPrabhakar Kushwaha #include <i2c.h> 107d436078SPrabhakar Kushwaha #include <netdev.h> 117d436078SPrabhakar Kushwaha #include <linux/compiler.h> 127d436078SPrabhakar Kushwaha #include <asm/mmu.h> 137d436078SPrabhakar Kushwaha #include <asm/processor.h> 147d436078SPrabhakar Kushwaha #include <asm/cache.h> 157d436078SPrabhakar Kushwaha #include <asm/immap_85xx.h> 167d436078SPrabhakar Kushwaha #include <asm/fsl_law.h> 177d436078SPrabhakar Kushwaha #include <asm/fsl_serdes.h> 187d436078SPrabhakar Kushwaha #include <asm/fsl_liodn.h> 197d436078SPrabhakar Kushwaha #include <fm_eth.h> 206259e291SZhao Qiang #include <hwconfig.h> 217d436078SPrabhakar Kushwaha 227d0e97a2Stang yuantian #include "../common/sleep.h" 237d436078SPrabhakar Kushwaha #include "../common/qixis.h" 247d436078SPrabhakar Kushwaha #include "t1040qds.h" 257d436078SPrabhakar Kushwaha #include "t1040qds_qixis.h" 267d436078SPrabhakar Kushwaha 277d436078SPrabhakar Kushwaha DECLARE_GLOBAL_DATA_PTR; 287d436078SPrabhakar Kushwaha 297d436078SPrabhakar Kushwaha int checkboard(void) 307d436078SPrabhakar Kushwaha { 317d436078SPrabhakar Kushwaha char buf[64]; 327d436078SPrabhakar Kushwaha u8 sw; 337d436078SPrabhakar Kushwaha struct cpu_type *cpu = gd->arch.cpu; 347d436078SPrabhakar Kushwaha static const char *const freq[] = {"100", "125", "156.25", "161.13", 357d436078SPrabhakar Kushwaha "122.88", "122.88", "122.88"}; 367d436078SPrabhakar Kushwaha int clock; 377d436078SPrabhakar Kushwaha 387d436078SPrabhakar Kushwaha printf("Board: %sQDS, ", cpu->name); 397d436078SPrabhakar Kushwaha printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ", 407d436078SPrabhakar Kushwaha QIXIS_READ(id), QIXIS_READ(arch)); 417d436078SPrabhakar Kushwaha 427d436078SPrabhakar Kushwaha sw = QIXIS_READ(brdcfg[0]); 437d436078SPrabhakar Kushwaha sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 447d436078SPrabhakar Kushwaha 457d436078SPrabhakar Kushwaha if (sw < 0x8) 467d436078SPrabhakar Kushwaha printf("vBank: %d\n", sw); 477d436078SPrabhakar Kushwaha else if (sw == 0x8) 487d436078SPrabhakar Kushwaha puts("PromJet\n"); 497d436078SPrabhakar Kushwaha else if (sw == 0x9) 507d436078SPrabhakar Kushwaha puts("NAND\n"); 517d436078SPrabhakar Kushwaha else if (sw == 0x15) 527d436078SPrabhakar Kushwaha printf("IFCCard\n"); 537d436078SPrabhakar Kushwaha else 547d436078SPrabhakar Kushwaha printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 557d436078SPrabhakar Kushwaha 567d436078SPrabhakar Kushwaha printf("FPGA: v%d (%s), build %d", 577d436078SPrabhakar Kushwaha (int)QIXIS_READ(scver), qixis_read_tag(buf), 587d436078SPrabhakar Kushwaha (int)qixis_read_minor()); 597d436078SPrabhakar Kushwaha /* the timestamp string contains "\n" at the end */ 607d436078SPrabhakar Kushwaha printf(" on %s", qixis_read_time(buf)); 617d436078SPrabhakar Kushwaha 627d436078SPrabhakar Kushwaha /* 637d436078SPrabhakar Kushwaha * Display the actual SERDES reference clocks as configured by the 647d436078SPrabhakar Kushwaha * dip switches on the board. Note that the SWx registers could 657d436078SPrabhakar Kushwaha * technically be set to force the reference clocks to match the 667d436078SPrabhakar Kushwaha * values that the SERDES expects (or vice versa). For now, however, 677d436078SPrabhakar Kushwaha * we just display both values and hope the user notices when they 687d436078SPrabhakar Kushwaha * don't match. 697d436078SPrabhakar Kushwaha */ 707d436078SPrabhakar Kushwaha puts("SERDES Reference: "); 717d436078SPrabhakar Kushwaha sw = QIXIS_READ(brdcfg[2]); 727d436078SPrabhakar Kushwaha clock = (sw >> 6) & 3; 737d436078SPrabhakar Kushwaha printf("Clock1=%sMHz ", freq[clock]); 747d436078SPrabhakar Kushwaha clock = (sw >> 4) & 3; 757d436078SPrabhakar Kushwaha printf("Clock2=%sMHz\n", freq[clock]); 767d436078SPrabhakar Kushwaha 777d436078SPrabhakar Kushwaha return 0; 787d436078SPrabhakar Kushwaha } 797d436078SPrabhakar Kushwaha 807d436078SPrabhakar Kushwaha int select_i2c_ch_pca9547(u8 ch) 817d436078SPrabhakar Kushwaha { 827d436078SPrabhakar Kushwaha int ret; 837d436078SPrabhakar Kushwaha 847d436078SPrabhakar Kushwaha ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); 857d436078SPrabhakar Kushwaha if (ret) { 867d436078SPrabhakar Kushwaha puts("PCA: failed to select proper channel\n"); 877d436078SPrabhakar Kushwaha return ret; 887d436078SPrabhakar Kushwaha } 897d436078SPrabhakar Kushwaha 907d436078SPrabhakar Kushwaha return 0; 917d436078SPrabhakar Kushwaha } 927d436078SPrabhakar Kushwaha 936259e291SZhao Qiang static void qe_board_setup(void) 946259e291SZhao Qiang { 956259e291SZhao Qiang u8 brdcfg15, brdcfg9; 966259e291SZhao Qiang 976259e291SZhao Qiang if (hwconfig("qe") && hwconfig("tdm")) { 986259e291SZhao Qiang brdcfg15 = QIXIS_READ(brdcfg[15]); 996259e291SZhao Qiang /* 1006259e291SZhao Qiang * TDMRiser uses QE-TDM 1016259e291SZhao Qiang * Route QE_TDM signals to TDM Riser slot 1026259e291SZhao Qiang */ 1036259e291SZhao Qiang QIXIS_WRITE(brdcfg[15], brdcfg15 | 7); 1046259e291SZhao Qiang } else if (hwconfig("qe") && hwconfig("uart")) { 1056259e291SZhao Qiang brdcfg15 = QIXIS_READ(brdcfg[15]); 1066259e291SZhao Qiang brdcfg9 = QIXIS_READ(brdcfg[9]); 1076259e291SZhao Qiang /* 1086259e291SZhao Qiang * Route QE_TDM signals to UCC 1096259e291SZhao Qiang * ProfiBus controlled by UCC3 1106259e291SZhao Qiang */ 1116259e291SZhao Qiang brdcfg15 &= 0xfc; 1126259e291SZhao Qiang QIXIS_WRITE(brdcfg[15], brdcfg15 | 2); 1136259e291SZhao Qiang QIXIS_WRITE(brdcfg[9], brdcfg9 | 4); 1146259e291SZhao Qiang } 1156259e291SZhao Qiang } 1166259e291SZhao Qiang 1177d0e97a2Stang yuantian int board_early_init_f(void) 1187d0e97a2Stang yuantian { 1197d0e97a2Stang yuantian #if defined(CONFIG_DEEP_SLEEP) 1207d0e97a2Stang yuantian if (is_warm_boot()) 1217d0e97a2Stang yuantian fsl_dp_disable_console(); 1227d0e97a2Stang yuantian #endif 1237d0e97a2Stang yuantian 1247d0e97a2Stang yuantian return 0; 1257d0e97a2Stang yuantian } 1267d0e97a2Stang yuantian 1277d436078SPrabhakar Kushwaha int board_early_init_r(void) 1287d436078SPrabhakar Kushwaha { 1297d436078SPrabhakar Kushwaha #ifdef CONFIG_SYS_FLASH_BASE 1307d436078SPrabhakar Kushwaha const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 1319d045682SYork Sun int flash_esel = find_tlb_idx((void *)flashbase, 1); 1327d436078SPrabhakar Kushwaha 1337d436078SPrabhakar Kushwaha /* 1347d436078SPrabhakar Kushwaha * Remap Boot flash + PROMJET region to caching-inhibited 1357d436078SPrabhakar Kushwaha * so that flash can be erased properly. 1367d436078SPrabhakar Kushwaha */ 1377d436078SPrabhakar Kushwaha 1387d436078SPrabhakar Kushwaha /* Flush d-cache and invalidate i-cache of any FLASH data */ 1397d436078SPrabhakar Kushwaha flush_dcache(); 1407d436078SPrabhakar Kushwaha invalidate_icache(); 1417d436078SPrabhakar Kushwaha 1429d045682SYork Sun if (flash_esel == -1) { 1439d045682SYork Sun /* very unlikely unless something is messed up */ 1449d045682SYork Sun puts("Error: Could not find TLB for FLASH BASE\n"); 1459d045682SYork Sun flash_esel = 2; /* give our best effort to continue */ 1469d045682SYork Sun } else { 1477d436078SPrabhakar Kushwaha /* invalidate existing TLB entry for flash + promjet */ 1487d436078SPrabhakar Kushwaha disable_tlb(flash_esel); 1499d045682SYork Sun } 1507d436078SPrabhakar Kushwaha 1517d436078SPrabhakar Kushwaha set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, 1527d436078SPrabhakar Kushwaha MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 1537d436078SPrabhakar Kushwaha 0, flash_esel, BOOKE_PAGESZ_256M, 1); 1547d436078SPrabhakar Kushwaha #endif 1557d436078SPrabhakar Kushwaha select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 1567d436078SPrabhakar Kushwaha 1577d436078SPrabhakar Kushwaha return 0; 1587d436078SPrabhakar Kushwaha } 1597d436078SPrabhakar Kushwaha 1607d436078SPrabhakar Kushwaha unsigned long get_board_sys_clk(void) 1617d436078SPrabhakar Kushwaha { 1627d436078SPrabhakar Kushwaha u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 1637d436078SPrabhakar Kushwaha 1647d436078SPrabhakar Kushwaha switch (sysclk_conf & 0x0F) { 1657d436078SPrabhakar Kushwaha case QIXIS_SYSCLK_64: 1667d436078SPrabhakar Kushwaha return 64000000; 1677d436078SPrabhakar Kushwaha case QIXIS_SYSCLK_83: 1687d436078SPrabhakar Kushwaha return 83333333; 1697d436078SPrabhakar Kushwaha case QIXIS_SYSCLK_100: 1707d436078SPrabhakar Kushwaha return 100000000; 1717d436078SPrabhakar Kushwaha case QIXIS_SYSCLK_125: 1727d436078SPrabhakar Kushwaha return 125000000; 1737d436078SPrabhakar Kushwaha case QIXIS_SYSCLK_133: 1747d436078SPrabhakar Kushwaha return 133333333; 1757d436078SPrabhakar Kushwaha case QIXIS_SYSCLK_150: 1767d436078SPrabhakar Kushwaha return 150000000; 1777d436078SPrabhakar Kushwaha case QIXIS_SYSCLK_160: 1787d436078SPrabhakar Kushwaha return 160000000; 1797d436078SPrabhakar Kushwaha case QIXIS_SYSCLK_166: 1807d436078SPrabhakar Kushwaha return 166666666; 1817d436078SPrabhakar Kushwaha } 1827d436078SPrabhakar Kushwaha return 66666666; 1837d436078SPrabhakar Kushwaha } 1847d436078SPrabhakar Kushwaha 1857d436078SPrabhakar Kushwaha unsigned long get_board_ddr_clk(void) 1867d436078SPrabhakar Kushwaha { 1877d436078SPrabhakar Kushwaha u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 1887d436078SPrabhakar Kushwaha 1897d436078SPrabhakar Kushwaha switch ((ddrclk_conf & 0x30) >> 4) { 1907d436078SPrabhakar Kushwaha case QIXIS_DDRCLK_100: 1917d436078SPrabhakar Kushwaha return 100000000; 1927d436078SPrabhakar Kushwaha case QIXIS_DDRCLK_125: 1937d436078SPrabhakar Kushwaha return 125000000; 1947d436078SPrabhakar Kushwaha case QIXIS_DDRCLK_133: 1957d436078SPrabhakar Kushwaha return 133333333; 1967d436078SPrabhakar Kushwaha } 1977d436078SPrabhakar Kushwaha return 66666666; 1987d436078SPrabhakar Kushwaha } 1997d436078SPrabhakar Kushwaha 2007d436078SPrabhakar Kushwaha #define NUM_SRDS_BANKS 2 2017d436078SPrabhakar Kushwaha int misc_init_r(void) 2027d436078SPrabhakar Kushwaha { 2037d436078SPrabhakar Kushwaha u8 sw; 2047d436078SPrabhakar Kushwaha serdes_corenet_t *srds_regs = 2057d436078SPrabhakar Kushwaha (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 2067d436078SPrabhakar Kushwaha u32 actual[NUM_SRDS_BANKS] = { 0 }; 2077d436078SPrabhakar Kushwaha int i; 2087d436078SPrabhakar Kushwaha 2097d436078SPrabhakar Kushwaha sw = QIXIS_READ(brdcfg[2]); 2107d436078SPrabhakar Kushwaha for (i = 0; i < NUM_SRDS_BANKS; i++) { 2117d436078SPrabhakar Kushwaha unsigned int clock = (sw >> (6 - 2 * i)) & 3; 2127d436078SPrabhakar Kushwaha switch (clock) { 2137d436078SPrabhakar Kushwaha case 0: 2147d436078SPrabhakar Kushwaha actual[i] = SRDS_PLLCR0_RFCK_SEL_100; 2157d436078SPrabhakar Kushwaha break; 2167d436078SPrabhakar Kushwaha case 1: 2177d436078SPrabhakar Kushwaha actual[i] = SRDS_PLLCR0_RFCK_SEL_125; 2187d436078SPrabhakar Kushwaha break; 2197d436078SPrabhakar Kushwaha case 2: 2207d436078SPrabhakar Kushwaha actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25; 2217d436078SPrabhakar Kushwaha break; 2227d436078SPrabhakar Kushwaha } 2237d436078SPrabhakar Kushwaha } 2247d436078SPrabhakar Kushwaha 2257d436078SPrabhakar Kushwaha puts("SerDes1"); 2267d436078SPrabhakar Kushwaha for (i = 0; i < NUM_SRDS_BANKS; i++) { 2277d436078SPrabhakar Kushwaha u32 pllcr0 = srds_regs->bank[i].pllcr0; 2287d436078SPrabhakar Kushwaha u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; 2297d436078SPrabhakar Kushwaha if (expected != actual[i]) { 2307d436078SPrabhakar Kushwaha printf("expects ref clk%d %sMHz, but actual is %sMHz\n", 2317d436078SPrabhakar Kushwaha i + 1, serdes_clock_to_string(expected), 2327d436078SPrabhakar Kushwaha serdes_clock_to_string(actual[i])); 2337d436078SPrabhakar Kushwaha } 2347d436078SPrabhakar Kushwaha } 2357d436078SPrabhakar Kushwaha 2366259e291SZhao Qiang qe_board_setup(); 2376259e291SZhao Qiang 2387d436078SPrabhakar Kushwaha return 0; 2397d436078SPrabhakar Kushwaha } 2407d436078SPrabhakar Kushwaha 241e895a4b0SSimon Glass int ft_board_setup(void *blob, bd_t *bd) 2427d436078SPrabhakar Kushwaha { 2437d436078SPrabhakar Kushwaha phys_addr_t base; 2447d436078SPrabhakar Kushwaha phys_size_t size; 2457d436078SPrabhakar Kushwaha 2467d436078SPrabhakar Kushwaha ft_cpu_setup(blob, bd); 2477d436078SPrabhakar Kushwaha 2487d436078SPrabhakar Kushwaha base = getenv_bootm_low(); 2497d436078SPrabhakar Kushwaha size = getenv_bootm_size(); 2507d436078SPrabhakar Kushwaha 2517d436078SPrabhakar Kushwaha fdt_fixup_memory(blob, (u64)base, (u64)size); 2527d436078SPrabhakar Kushwaha 2537d436078SPrabhakar Kushwaha #ifdef CONFIG_PCI 2547d436078SPrabhakar Kushwaha pci_of_setup(blob, bd); 2557d436078SPrabhakar Kushwaha #endif 2567d436078SPrabhakar Kushwaha 2577d436078SPrabhakar Kushwaha fdt_fixup_liodn(blob); 2587d436078SPrabhakar Kushwaha 2597d436078SPrabhakar Kushwaha #ifdef CONFIG_HAS_FSL_DR_USB 260*a5c289b9SSriram Dash fsl_fdt_fixup_dr_usb(blob, bd); 2617d436078SPrabhakar Kushwaha #endif 2627d436078SPrabhakar Kushwaha 2637d436078SPrabhakar Kushwaha #ifdef CONFIG_SYS_DPAA_FMAN 2647d436078SPrabhakar Kushwaha fdt_fixup_fman_ethernet(blob); 2655b7672fcSPrabhakar Kushwaha fdt_fixup_board_enet(blob); 2667d436078SPrabhakar Kushwaha #endif 267e895a4b0SSimon Glass 268e895a4b0SSimon Glass return 0; 2697d436078SPrabhakar Kushwaha } 2707d436078SPrabhakar Kushwaha 2717d436078SPrabhakar Kushwaha void qixis_dump_switch(void) 2727d436078SPrabhakar Kushwaha { 2737d436078SPrabhakar Kushwaha int i, nr_of_cfgsw; 2747d436078SPrabhakar Kushwaha 2757d436078SPrabhakar Kushwaha QIXIS_WRITE(cms[0], 0x00); 2767d436078SPrabhakar Kushwaha nr_of_cfgsw = QIXIS_READ(cms[1]); 2777d436078SPrabhakar Kushwaha 2787d436078SPrabhakar Kushwaha puts("DIP switch settings dump:\n"); 2797d436078SPrabhakar Kushwaha for (i = 1; i <= nr_of_cfgsw; i++) { 2807d436078SPrabhakar Kushwaha QIXIS_WRITE(cms[0], i); 2817d436078SPrabhakar Kushwaha printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); 2827d436078SPrabhakar Kushwaha } 2837d436078SPrabhakar Kushwaha } 2848c618dd6SPrabhakar Kushwaha 2858c618dd6SPrabhakar Kushwaha int board_need_mem_reset(void) 2868c618dd6SPrabhakar Kushwaha { 2878c618dd6SPrabhakar Kushwaha return 1; 2888c618dd6SPrabhakar Kushwaha } 289