17d436078SPrabhakar Kushwaha /* 27d436078SPrabhakar Kushwaha * Copyright 2013 Freescale Semiconductor, Inc. 37d436078SPrabhakar Kushwaha * 47d436078SPrabhakar Kushwaha * SPDX-License-Identifier: GPL-2.0+ 57d436078SPrabhakar Kushwaha */ 67d436078SPrabhakar Kushwaha 77d436078SPrabhakar Kushwaha #include <common.h> 87d436078SPrabhakar Kushwaha #include <command.h> 97d436078SPrabhakar Kushwaha #include <i2c.h> 107d436078SPrabhakar Kushwaha #include <netdev.h> 117d436078SPrabhakar Kushwaha #include <linux/compiler.h> 127d436078SPrabhakar Kushwaha #include <asm/mmu.h> 137d436078SPrabhakar Kushwaha #include <asm/processor.h> 147d436078SPrabhakar Kushwaha #include <asm/cache.h> 157d436078SPrabhakar Kushwaha #include <asm/immap_85xx.h> 167d436078SPrabhakar Kushwaha #include <asm/fsl_law.h> 177d436078SPrabhakar Kushwaha #include <asm/fsl_serdes.h> 187d436078SPrabhakar Kushwaha #include <asm/fsl_portals.h> 197d436078SPrabhakar Kushwaha #include <asm/fsl_liodn.h> 207d436078SPrabhakar Kushwaha #include <fm_eth.h> 216259e291SZhao Qiang #include <hwconfig.h> 2248f6a9a2STang Yuantian #include <asm/mpc85xx_gpio.h> 237d436078SPrabhakar Kushwaha 247d436078SPrabhakar Kushwaha #include "../common/qixis.h" 257d436078SPrabhakar Kushwaha #include "t1040qds.h" 267d436078SPrabhakar Kushwaha #include "t1040qds_qixis.h" 277d436078SPrabhakar Kushwaha 287d436078SPrabhakar Kushwaha DECLARE_GLOBAL_DATA_PTR; 297d436078SPrabhakar Kushwaha 307d436078SPrabhakar Kushwaha int checkboard(void) 317d436078SPrabhakar Kushwaha { 327d436078SPrabhakar Kushwaha char buf[64]; 337d436078SPrabhakar Kushwaha u8 sw; 347d436078SPrabhakar Kushwaha struct cpu_type *cpu = gd->arch.cpu; 357d436078SPrabhakar Kushwaha static const char *const freq[] = {"100", "125", "156.25", "161.13", 367d436078SPrabhakar Kushwaha "122.88", "122.88", "122.88"}; 377d436078SPrabhakar Kushwaha int clock; 387d436078SPrabhakar Kushwaha 397d436078SPrabhakar Kushwaha printf("Board: %sQDS, ", cpu->name); 407d436078SPrabhakar Kushwaha printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ", 417d436078SPrabhakar Kushwaha QIXIS_READ(id), QIXIS_READ(arch)); 427d436078SPrabhakar Kushwaha 437d436078SPrabhakar Kushwaha sw = QIXIS_READ(brdcfg[0]); 447d436078SPrabhakar Kushwaha sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 457d436078SPrabhakar Kushwaha 467d436078SPrabhakar Kushwaha if (sw < 0x8) 477d436078SPrabhakar Kushwaha printf("vBank: %d\n", sw); 487d436078SPrabhakar Kushwaha else if (sw == 0x8) 497d436078SPrabhakar Kushwaha puts("PromJet\n"); 507d436078SPrabhakar Kushwaha else if (sw == 0x9) 517d436078SPrabhakar Kushwaha puts("NAND\n"); 527d436078SPrabhakar Kushwaha else if (sw == 0x15) 537d436078SPrabhakar Kushwaha printf("IFCCard\n"); 547d436078SPrabhakar Kushwaha else 557d436078SPrabhakar Kushwaha printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 567d436078SPrabhakar Kushwaha 577d436078SPrabhakar Kushwaha printf("FPGA: v%d (%s), build %d", 587d436078SPrabhakar Kushwaha (int)QIXIS_READ(scver), qixis_read_tag(buf), 597d436078SPrabhakar Kushwaha (int)qixis_read_minor()); 607d436078SPrabhakar Kushwaha /* the timestamp string contains "\n" at the end */ 617d436078SPrabhakar Kushwaha printf(" on %s", qixis_read_time(buf)); 627d436078SPrabhakar Kushwaha 637d436078SPrabhakar Kushwaha /* 647d436078SPrabhakar Kushwaha * Display the actual SERDES reference clocks as configured by the 657d436078SPrabhakar Kushwaha * dip switches on the board. Note that the SWx registers could 667d436078SPrabhakar Kushwaha * technically be set to force the reference clocks to match the 677d436078SPrabhakar Kushwaha * values that the SERDES expects (or vice versa). For now, however, 687d436078SPrabhakar Kushwaha * we just display both values and hope the user notices when they 697d436078SPrabhakar Kushwaha * don't match. 707d436078SPrabhakar Kushwaha */ 717d436078SPrabhakar Kushwaha puts("SERDES Reference: "); 727d436078SPrabhakar Kushwaha sw = QIXIS_READ(brdcfg[2]); 737d436078SPrabhakar Kushwaha clock = (sw >> 6) & 3; 747d436078SPrabhakar Kushwaha printf("Clock1=%sMHz ", freq[clock]); 757d436078SPrabhakar Kushwaha clock = (sw >> 4) & 3; 767d436078SPrabhakar Kushwaha printf("Clock2=%sMHz\n", freq[clock]); 777d436078SPrabhakar Kushwaha 787d436078SPrabhakar Kushwaha return 0; 797d436078SPrabhakar Kushwaha } 807d436078SPrabhakar Kushwaha 817d436078SPrabhakar Kushwaha int select_i2c_ch_pca9547(u8 ch) 827d436078SPrabhakar Kushwaha { 837d436078SPrabhakar Kushwaha int ret; 847d436078SPrabhakar Kushwaha 857d436078SPrabhakar Kushwaha ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); 867d436078SPrabhakar Kushwaha if (ret) { 877d436078SPrabhakar Kushwaha puts("PCA: failed to select proper channel\n"); 887d436078SPrabhakar Kushwaha return ret; 897d436078SPrabhakar Kushwaha } 907d436078SPrabhakar Kushwaha 917d436078SPrabhakar Kushwaha return 0; 927d436078SPrabhakar Kushwaha } 937d436078SPrabhakar Kushwaha 946259e291SZhao Qiang static void qe_board_setup(void) 956259e291SZhao Qiang { 966259e291SZhao Qiang u8 brdcfg15, brdcfg9; 976259e291SZhao Qiang 986259e291SZhao Qiang if (hwconfig("qe") && hwconfig("tdm")) { 996259e291SZhao Qiang brdcfg15 = QIXIS_READ(brdcfg[15]); 1006259e291SZhao Qiang /* 1016259e291SZhao Qiang * TDMRiser uses QE-TDM 1026259e291SZhao Qiang * Route QE_TDM signals to TDM Riser slot 1036259e291SZhao Qiang */ 1046259e291SZhao Qiang QIXIS_WRITE(brdcfg[15], brdcfg15 | 7); 1056259e291SZhao Qiang } else if (hwconfig("qe") && hwconfig("uart")) { 1066259e291SZhao Qiang brdcfg15 = QIXIS_READ(brdcfg[15]); 1076259e291SZhao Qiang brdcfg9 = QIXIS_READ(brdcfg[9]); 1086259e291SZhao Qiang /* 1096259e291SZhao Qiang * Route QE_TDM signals to UCC 1106259e291SZhao Qiang * ProfiBus controlled by UCC3 1116259e291SZhao Qiang */ 1126259e291SZhao Qiang brdcfg15 &= 0xfc; 1136259e291SZhao Qiang QIXIS_WRITE(brdcfg[15], brdcfg15 | 2); 1146259e291SZhao Qiang QIXIS_WRITE(brdcfg[9], brdcfg9 | 4); 1156259e291SZhao Qiang } 1166259e291SZhao Qiang } 1176259e291SZhao Qiang 1187d436078SPrabhakar Kushwaha int board_early_init_r(void) 1197d436078SPrabhakar Kushwaha { 1207d436078SPrabhakar Kushwaha #ifdef CONFIG_SYS_FLASH_BASE 1217d436078SPrabhakar Kushwaha const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 122*9d045682SYork Sun int flash_esel = find_tlb_idx((void *)flashbase, 1); 1237d436078SPrabhakar Kushwaha 1247d436078SPrabhakar Kushwaha /* 1257d436078SPrabhakar Kushwaha * Remap Boot flash + PROMJET region to caching-inhibited 1267d436078SPrabhakar Kushwaha * so that flash can be erased properly. 1277d436078SPrabhakar Kushwaha */ 1287d436078SPrabhakar Kushwaha 1297d436078SPrabhakar Kushwaha /* Flush d-cache and invalidate i-cache of any FLASH data */ 1307d436078SPrabhakar Kushwaha flush_dcache(); 1317d436078SPrabhakar Kushwaha invalidate_icache(); 1327d436078SPrabhakar Kushwaha 133*9d045682SYork Sun if (flash_esel == -1) { 134*9d045682SYork Sun /* very unlikely unless something is messed up */ 135*9d045682SYork Sun puts("Error: Could not find TLB for FLASH BASE\n"); 136*9d045682SYork Sun flash_esel = 2; /* give our best effort to continue */ 137*9d045682SYork Sun } else { 1387d436078SPrabhakar Kushwaha /* invalidate existing TLB entry for flash + promjet */ 1397d436078SPrabhakar Kushwaha disable_tlb(flash_esel); 140*9d045682SYork Sun } 1417d436078SPrabhakar Kushwaha 1427d436078SPrabhakar Kushwaha set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, 1437d436078SPrabhakar Kushwaha MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 1447d436078SPrabhakar Kushwaha 0, flash_esel, BOOKE_PAGESZ_256M, 1); 1457d436078SPrabhakar Kushwaha #endif 1467d436078SPrabhakar Kushwaha set_liodns(); 1477d436078SPrabhakar Kushwaha #ifdef CONFIG_SYS_DPAA_QBMAN 1487d436078SPrabhakar Kushwaha setup_portals(); 1497d436078SPrabhakar Kushwaha #endif 1507d436078SPrabhakar Kushwaha select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 1517d436078SPrabhakar Kushwaha 1527d436078SPrabhakar Kushwaha return 0; 1537d436078SPrabhakar Kushwaha } 1547d436078SPrabhakar Kushwaha 1557d436078SPrabhakar Kushwaha unsigned long get_board_sys_clk(void) 1567d436078SPrabhakar Kushwaha { 1577d436078SPrabhakar Kushwaha u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 1587d436078SPrabhakar Kushwaha 1597d436078SPrabhakar Kushwaha switch (sysclk_conf & 0x0F) { 1607d436078SPrabhakar Kushwaha case QIXIS_SYSCLK_64: 1617d436078SPrabhakar Kushwaha return 64000000; 1627d436078SPrabhakar Kushwaha case QIXIS_SYSCLK_83: 1637d436078SPrabhakar Kushwaha return 83333333; 1647d436078SPrabhakar Kushwaha case QIXIS_SYSCLK_100: 1657d436078SPrabhakar Kushwaha return 100000000; 1667d436078SPrabhakar Kushwaha case QIXIS_SYSCLK_125: 1677d436078SPrabhakar Kushwaha return 125000000; 1687d436078SPrabhakar Kushwaha case QIXIS_SYSCLK_133: 1697d436078SPrabhakar Kushwaha return 133333333; 1707d436078SPrabhakar Kushwaha case QIXIS_SYSCLK_150: 1717d436078SPrabhakar Kushwaha return 150000000; 1727d436078SPrabhakar Kushwaha case QIXIS_SYSCLK_160: 1737d436078SPrabhakar Kushwaha return 160000000; 1747d436078SPrabhakar Kushwaha case QIXIS_SYSCLK_166: 1757d436078SPrabhakar Kushwaha return 166666666; 1767d436078SPrabhakar Kushwaha } 1777d436078SPrabhakar Kushwaha return 66666666; 1787d436078SPrabhakar Kushwaha } 1797d436078SPrabhakar Kushwaha 1807d436078SPrabhakar Kushwaha unsigned long get_board_ddr_clk(void) 1817d436078SPrabhakar Kushwaha { 1827d436078SPrabhakar Kushwaha u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 1837d436078SPrabhakar Kushwaha 1847d436078SPrabhakar Kushwaha switch ((ddrclk_conf & 0x30) >> 4) { 1857d436078SPrabhakar Kushwaha case QIXIS_DDRCLK_100: 1867d436078SPrabhakar Kushwaha return 100000000; 1877d436078SPrabhakar Kushwaha case QIXIS_DDRCLK_125: 1887d436078SPrabhakar Kushwaha return 125000000; 1897d436078SPrabhakar Kushwaha case QIXIS_DDRCLK_133: 1907d436078SPrabhakar Kushwaha return 133333333; 1917d436078SPrabhakar Kushwaha } 1927d436078SPrabhakar Kushwaha return 66666666; 1937d436078SPrabhakar Kushwaha } 1947d436078SPrabhakar Kushwaha 1957d436078SPrabhakar Kushwaha #define NUM_SRDS_BANKS 2 1967d436078SPrabhakar Kushwaha int misc_init_r(void) 1977d436078SPrabhakar Kushwaha { 1987d436078SPrabhakar Kushwaha u8 sw; 1997d436078SPrabhakar Kushwaha serdes_corenet_t *srds_regs = 2007d436078SPrabhakar Kushwaha (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 2017d436078SPrabhakar Kushwaha u32 actual[NUM_SRDS_BANKS] = { 0 }; 2027d436078SPrabhakar Kushwaha int i; 2037d436078SPrabhakar Kushwaha 2047d436078SPrabhakar Kushwaha sw = QIXIS_READ(brdcfg[2]); 2057d436078SPrabhakar Kushwaha for (i = 0; i < NUM_SRDS_BANKS; i++) { 2067d436078SPrabhakar Kushwaha unsigned int clock = (sw >> (6 - 2 * i)) & 3; 2077d436078SPrabhakar Kushwaha switch (clock) { 2087d436078SPrabhakar Kushwaha case 0: 2097d436078SPrabhakar Kushwaha actual[i] = SRDS_PLLCR0_RFCK_SEL_100; 2107d436078SPrabhakar Kushwaha break; 2117d436078SPrabhakar Kushwaha case 1: 2127d436078SPrabhakar Kushwaha actual[i] = SRDS_PLLCR0_RFCK_SEL_125; 2137d436078SPrabhakar Kushwaha break; 2147d436078SPrabhakar Kushwaha case 2: 2157d436078SPrabhakar Kushwaha actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25; 2167d436078SPrabhakar Kushwaha break; 2177d436078SPrabhakar Kushwaha } 2187d436078SPrabhakar Kushwaha } 2197d436078SPrabhakar Kushwaha 2207d436078SPrabhakar Kushwaha puts("SerDes1"); 2217d436078SPrabhakar Kushwaha for (i = 0; i < NUM_SRDS_BANKS; i++) { 2227d436078SPrabhakar Kushwaha u32 pllcr0 = srds_regs->bank[i].pllcr0; 2237d436078SPrabhakar Kushwaha u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; 2247d436078SPrabhakar Kushwaha if (expected != actual[i]) { 2257d436078SPrabhakar Kushwaha printf("expects ref clk%d %sMHz, but actual is %sMHz\n", 2267d436078SPrabhakar Kushwaha i + 1, serdes_clock_to_string(expected), 2277d436078SPrabhakar Kushwaha serdes_clock_to_string(actual[i])); 2287d436078SPrabhakar Kushwaha } 2297d436078SPrabhakar Kushwaha } 2307d436078SPrabhakar Kushwaha 2316259e291SZhao Qiang qe_board_setup(); 2326259e291SZhao Qiang 2337d436078SPrabhakar Kushwaha return 0; 2347d436078SPrabhakar Kushwaha } 2357d436078SPrabhakar Kushwaha 2367d436078SPrabhakar Kushwaha void ft_board_setup(void *blob, bd_t *bd) 2377d436078SPrabhakar Kushwaha { 2387d436078SPrabhakar Kushwaha phys_addr_t base; 2397d436078SPrabhakar Kushwaha phys_size_t size; 2407d436078SPrabhakar Kushwaha 2417d436078SPrabhakar Kushwaha ft_cpu_setup(blob, bd); 2427d436078SPrabhakar Kushwaha 2437d436078SPrabhakar Kushwaha base = getenv_bootm_low(); 2447d436078SPrabhakar Kushwaha size = getenv_bootm_size(); 2457d436078SPrabhakar Kushwaha 2467d436078SPrabhakar Kushwaha fdt_fixup_memory(blob, (u64)base, (u64)size); 2477d436078SPrabhakar Kushwaha 2487d436078SPrabhakar Kushwaha #ifdef CONFIG_PCI 2497d436078SPrabhakar Kushwaha pci_of_setup(blob, bd); 2507d436078SPrabhakar Kushwaha #endif 2517d436078SPrabhakar Kushwaha 2527d436078SPrabhakar Kushwaha fdt_fixup_liodn(blob); 2537d436078SPrabhakar Kushwaha 2547d436078SPrabhakar Kushwaha #ifdef CONFIG_HAS_FSL_DR_USB 2557d436078SPrabhakar Kushwaha fdt_fixup_dr_usb(blob, bd); 2567d436078SPrabhakar Kushwaha #endif 2577d436078SPrabhakar Kushwaha 2587d436078SPrabhakar Kushwaha #ifdef CONFIG_SYS_DPAA_FMAN 2597d436078SPrabhakar Kushwaha fdt_fixup_fman_ethernet(blob); 2605b7672fcSPrabhakar Kushwaha fdt_fixup_board_enet(blob); 2617d436078SPrabhakar Kushwaha #endif 2627d436078SPrabhakar Kushwaha } 2637d436078SPrabhakar Kushwaha 2647d436078SPrabhakar Kushwaha void qixis_dump_switch(void) 2657d436078SPrabhakar Kushwaha { 2667d436078SPrabhakar Kushwaha int i, nr_of_cfgsw; 2677d436078SPrabhakar Kushwaha 2687d436078SPrabhakar Kushwaha QIXIS_WRITE(cms[0], 0x00); 2697d436078SPrabhakar Kushwaha nr_of_cfgsw = QIXIS_READ(cms[1]); 2707d436078SPrabhakar Kushwaha 2717d436078SPrabhakar Kushwaha puts("DIP switch settings dump:\n"); 2727d436078SPrabhakar Kushwaha for (i = 1; i <= nr_of_cfgsw; i++) { 2737d436078SPrabhakar Kushwaha QIXIS_WRITE(cms[0], i); 2747d436078SPrabhakar Kushwaha printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); 2757d436078SPrabhakar Kushwaha } 2767d436078SPrabhakar Kushwaha } 2778c618dd6SPrabhakar Kushwaha 2788c618dd6SPrabhakar Kushwaha int board_need_mem_reset(void) 2798c618dd6SPrabhakar Kushwaha { 2808c618dd6SPrabhakar Kushwaha return 1; 2818c618dd6SPrabhakar Kushwaha } 28248f6a9a2STang Yuantian 28348f6a9a2STang Yuantian #ifdef CONFIG_DEEP_SLEEP 28448f6a9a2STang Yuantian void board_mem_sleep_setup(void) 28548f6a9a2STang Yuantian { 28648f6a9a2STang Yuantian /* does not provide HW signals for power management */ 28748f6a9a2STang Yuantian QIXIS_WRITE(pwr_ctl[1], (QIXIS_READ(pwr_ctl[1]) & ~0x2)); 28848f6a9a2STang Yuantian /* Disable MCKE isolation */ 28948f6a9a2STang Yuantian gpio_set_value(2, 0); 29048f6a9a2STang Yuantian udelay(1); 29148f6a9a2STang Yuantian } 29248f6a9a2STang Yuantian #endif 293