1*7d436078SPrabhakar Kushwaha /* 2*7d436078SPrabhakar Kushwaha * Copyright 2013 Freescale Semiconductor, Inc. 3*7d436078SPrabhakar Kushwaha * 4*7d436078SPrabhakar Kushwaha * SPDX-License-Identifier: GPL-2.0+ 5*7d436078SPrabhakar Kushwaha */ 6*7d436078SPrabhakar Kushwaha 7*7d436078SPrabhakar Kushwaha #include <common.h> 8*7d436078SPrabhakar Kushwaha #include <command.h> 9*7d436078SPrabhakar Kushwaha #include <i2c.h> 10*7d436078SPrabhakar Kushwaha #include <netdev.h> 11*7d436078SPrabhakar Kushwaha #include <linux/compiler.h> 12*7d436078SPrabhakar Kushwaha #include <asm/mmu.h> 13*7d436078SPrabhakar Kushwaha #include <asm/processor.h> 14*7d436078SPrabhakar Kushwaha #include <asm/cache.h> 15*7d436078SPrabhakar Kushwaha #include <asm/immap_85xx.h> 16*7d436078SPrabhakar Kushwaha #include <asm/fsl_law.h> 17*7d436078SPrabhakar Kushwaha #include <asm/fsl_serdes.h> 18*7d436078SPrabhakar Kushwaha #include <asm/fsl_portals.h> 19*7d436078SPrabhakar Kushwaha #include <asm/fsl_liodn.h> 20*7d436078SPrabhakar Kushwaha #include <fm_eth.h> 21*7d436078SPrabhakar Kushwaha 22*7d436078SPrabhakar Kushwaha #include "../common/qixis.h" 23*7d436078SPrabhakar Kushwaha #include "t1040qds.h" 24*7d436078SPrabhakar Kushwaha #include "t1040qds_qixis.h" 25*7d436078SPrabhakar Kushwaha 26*7d436078SPrabhakar Kushwaha DECLARE_GLOBAL_DATA_PTR; 27*7d436078SPrabhakar Kushwaha 28*7d436078SPrabhakar Kushwaha int checkboard(void) 29*7d436078SPrabhakar Kushwaha { 30*7d436078SPrabhakar Kushwaha char buf[64]; 31*7d436078SPrabhakar Kushwaha u8 sw; 32*7d436078SPrabhakar Kushwaha struct cpu_type *cpu = gd->arch.cpu; 33*7d436078SPrabhakar Kushwaha static const char *const freq[] = {"100", "125", "156.25", "161.13", 34*7d436078SPrabhakar Kushwaha "122.88", "122.88", "122.88"}; 35*7d436078SPrabhakar Kushwaha int clock; 36*7d436078SPrabhakar Kushwaha 37*7d436078SPrabhakar Kushwaha printf("Board: %sQDS, ", cpu->name); 38*7d436078SPrabhakar Kushwaha printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ", 39*7d436078SPrabhakar Kushwaha QIXIS_READ(id), QIXIS_READ(arch)); 40*7d436078SPrabhakar Kushwaha 41*7d436078SPrabhakar Kushwaha sw = QIXIS_READ(brdcfg[0]); 42*7d436078SPrabhakar Kushwaha sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 43*7d436078SPrabhakar Kushwaha 44*7d436078SPrabhakar Kushwaha if (sw < 0x8) 45*7d436078SPrabhakar Kushwaha printf("vBank: %d\n", sw); 46*7d436078SPrabhakar Kushwaha else if (sw == 0x8) 47*7d436078SPrabhakar Kushwaha puts("PromJet\n"); 48*7d436078SPrabhakar Kushwaha else if (sw == 0x9) 49*7d436078SPrabhakar Kushwaha puts("NAND\n"); 50*7d436078SPrabhakar Kushwaha else if (sw == 0x15) 51*7d436078SPrabhakar Kushwaha printf("IFCCard\n"); 52*7d436078SPrabhakar Kushwaha else 53*7d436078SPrabhakar Kushwaha printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 54*7d436078SPrabhakar Kushwaha 55*7d436078SPrabhakar Kushwaha printf("FPGA: v%d (%s), build %d", 56*7d436078SPrabhakar Kushwaha (int)QIXIS_READ(scver), qixis_read_tag(buf), 57*7d436078SPrabhakar Kushwaha (int)qixis_read_minor()); 58*7d436078SPrabhakar Kushwaha /* the timestamp string contains "\n" at the end */ 59*7d436078SPrabhakar Kushwaha printf(" on %s", qixis_read_time(buf)); 60*7d436078SPrabhakar Kushwaha 61*7d436078SPrabhakar Kushwaha /* 62*7d436078SPrabhakar Kushwaha * Display the actual SERDES reference clocks as configured by the 63*7d436078SPrabhakar Kushwaha * dip switches on the board. Note that the SWx registers could 64*7d436078SPrabhakar Kushwaha * technically be set to force the reference clocks to match the 65*7d436078SPrabhakar Kushwaha * values that the SERDES expects (or vice versa). For now, however, 66*7d436078SPrabhakar Kushwaha * we just display both values and hope the user notices when they 67*7d436078SPrabhakar Kushwaha * don't match. 68*7d436078SPrabhakar Kushwaha */ 69*7d436078SPrabhakar Kushwaha puts("SERDES Reference: "); 70*7d436078SPrabhakar Kushwaha sw = QIXIS_READ(brdcfg[2]); 71*7d436078SPrabhakar Kushwaha clock = (sw >> 6) & 3; 72*7d436078SPrabhakar Kushwaha printf("Clock1=%sMHz ", freq[clock]); 73*7d436078SPrabhakar Kushwaha clock = (sw >> 4) & 3; 74*7d436078SPrabhakar Kushwaha printf("Clock2=%sMHz\n", freq[clock]); 75*7d436078SPrabhakar Kushwaha 76*7d436078SPrabhakar Kushwaha return 0; 77*7d436078SPrabhakar Kushwaha } 78*7d436078SPrabhakar Kushwaha 79*7d436078SPrabhakar Kushwaha int select_i2c_ch_pca9547(u8 ch) 80*7d436078SPrabhakar Kushwaha { 81*7d436078SPrabhakar Kushwaha int ret; 82*7d436078SPrabhakar Kushwaha 83*7d436078SPrabhakar Kushwaha ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); 84*7d436078SPrabhakar Kushwaha if (ret) { 85*7d436078SPrabhakar Kushwaha puts("PCA: failed to select proper channel\n"); 86*7d436078SPrabhakar Kushwaha return ret; 87*7d436078SPrabhakar Kushwaha } 88*7d436078SPrabhakar Kushwaha 89*7d436078SPrabhakar Kushwaha return 0; 90*7d436078SPrabhakar Kushwaha } 91*7d436078SPrabhakar Kushwaha 92*7d436078SPrabhakar Kushwaha int board_early_init_r(void) 93*7d436078SPrabhakar Kushwaha { 94*7d436078SPrabhakar Kushwaha #ifdef CONFIG_SYS_FLASH_BASE 95*7d436078SPrabhakar Kushwaha const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 96*7d436078SPrabhakar Kushwaha const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); 97*7d436078SPrabhakar Kushwaha 98*7d436078SPrabhakar Kushwaha /* 99*7d436078SPrabhakar Kushwaha * Remap Boot flash + PROMJET region to caching-inhibited 100*7d436078SPrabhakar Kushwaha * so that flash can be erased properly. 101*7d436078SPrabhakar Kushwaha */ 102*7d436078SPrabhakar Kushwaha 103*7d436078SPrabhakar Kushwaha /* Flush d-cache and invalidate i-cache of any FLASH data */ 104*7d436078SPrabhakar Kushwaha flush_dcache(); 105*7d436078SPrabhakar Kushwaha invalidate_icache(); 106*7d436078SPrabhakar Kushwaha 107*7d436078SPrabhakar Kushwaha /* invalidate existing TLB entry for flash + promjet */ 108*7d436078SPrabhakar Kushwaha disable_tlb(flash_esel); 109*7d436078SPrabhakar Kushwaha 110*7d436078SPrabhakar Kushwaha set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, 111*7d436078SPrabhakar Kushwaha MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 112*7d436078SPrabhakar Kushwaha 0, flash_esel, BOOKE_PAGESZ_256M, 1); 113*7d436078SPrabhakar Kushwaha #endif 114*7d436078SPrabhakar Kushwaha set_liodns(); 115*7d436078SPrabhakar Kushwaha #ifdef CONFIG_SYS_DPAA_QBMAN 116*7d436078SPrabhakar Kushwaha setup_portals(); 117*7d436078SPrabhakar Kushwaha #endif 118*7d436078SPrabhakar Kushwaha select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 119*7d436078SPrabhakar Kushwaha 120*7d436078SPrabhakar Kushwaha return 0; 121*7d436078SPrabhakar Kushwaha } 122*7d436078SPrabhakar Kushwaha 123*7d436078SPrabhakar Kushwaha unsigned long get_board_sys_clk(void) 124*7d436078SPrabhakar Kushwaha { 125*7d436078SPrabhakar Kushwaha u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 126*7d436078SPrabhakar Kushwaha 127*7d436078SPrabhakar Kushwaha switch (sysclk_conf & 0x0F) { 128*7d436078SPrabhakar Kushwaha case QIXIS_SYSCLK_64: 129*7d436078SPrabhakar Kushwaha return 64000000; 130*7d436078SPrabhakar Kushwaha case QIXIS_SYSCLK_83: 131*7d436078SPrabhakar Kushwaha return 83333333; 132*7d436078SPrabhakar Kushwaha case QIXIS_SYSCLK_100: 133*7d436078SPrabhakar Kushwaha return 100000000; 134*7d436078SPrabhakar Kushwaha case QIXIS_SYSCLK_125: 135*7d436078SPrabhakar Kushwaha return 125000000; 136*7d436078SPrabhakar Kushwaha case QIXIS_SYSCLK_133: 137*7d436078SPrabhakar Kushwaha return 133333333; 138*7d436078SPrabhakar Kushwaha case QIXIS_SYSCLK_150: 139*7d436078SPrabhakar Kushwaha return 150000000; 140*7d436078SPrabhakar Kushwaha case QIXIS_SYSCLK_160: 141*7d436078SPrabhakar Kushwaha return 160000000; 142*7d436078SPrabhakar Kushwaha case QIXIS_SYSCLK_166: 143*7d436078SPrabhakar Kushwaha return 166666666; 144*7d436078SPrabhakar Kushwaha } 145*7d436078SPrabhakar Kushwaha return 66666666; 146*7d436078SPrabhakar Kushwaha } 147*7d436078SPrabhakar Kushwaha 148*7d436078SPrabhakar Kushwaha unsigned long get_board_ddr_clk(void) 149*7d436078SPrabhakar Kushwaha { 150*7d436078SPrabhakar Kushwaha u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 151*7d436078SPrabhakar Kushwaha 152*7d436078SPrabhakar Kushwaha switch ((ddrclk_conf & 0x30) >> 4) { 153*7d436078SPrabhakar Kushwaha case QIXIS_DDRCLK_100: 154*7d436078SPrabhakar Kushwaha return 100000000; 155*7d436078SPrabhakar Kushwaha case QIXIS_DDRCLK_125: 156*7d436078SPrabhakar Kushwaha return 125000000; 157*7d436078SPrabhakar Kushwaha case QIXIS_DDRCLK_133: 158*7d436078SPrabhakar Kushwaha return 133333333; 159*7d436078SPrabhakar Kushwaha } 160*7d436078SPrabhakar Kushwaha return 66666666; 161*7d436078SPrabhakar Kushwaha } 162*7d436078SPrabhakar Kushwaha 163*7d436078SPrabhakar Kushwaha static const char *serdes_clock_to_string(u32 clock) 164*7d436078SPrabhakar Kushwaha { 165*7d436078SPrabhakar Kushwaha switch (clock) { 166*7d436078SPrabhakar Kushwaha case SRDS_PLLCR0_RFCK_SEL_100: 167*7d436078SPrabhakar Kushwaha return "100"; 168*7d436078SPrabhakar Kushwaha case SRDS_PLLCR0_RFCK_SEL_125: 169*7d436078SPrabhakar Kushwaha return "125"; 170*7d436078SPrabhakar Kushwaha case SRDS_PLLCR0_RFCK_SEL_156_25: 171*7d436078SPrabhakar Kushwaha return "156.25"; 172*7d436078SPrabhakar Kushwaha default: 173*7d436078SPrabhakar Kushwaha return "Unknown frequency"; 174*7d436078SPrabhakar Kushwaha } 175*7d436078SPrabhakar Kushwaha } 176*7d436078SPrabhakar Kushwaha 177*7d436078SPrabhakar Kushwaha #define NUM_SRDS_BANKS 2 178*7d436078SPrabhakar Kushwaha int misc_init_r(void) 179*7d436078SPrabhakar Kushwaha { 180*7d436078SPrabhakar Kushwaha u8 sw; 181*7d436078SPrabhakar Kushwaha serdes_corenet_t *srds_regs = 182*7d436078SPrabhakar Kushwaha (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 183*7d436078SPrabhakar Kushwaha u32 actual[NUM_SRDS_BANKS] = { 0 }; 184*7d436078SPrabhakar Kushwaha int i; 185*7d436078SPrabhakar Kushwaha 186*7d436078SPrabhakar Kushwaha sw = QIXIS_READ(brdcfg[2]); 187*7d436078SPrabhakar Kushwaha for (i = 0; i < NUM_SRDS_BANKS; i++) { 188*7d436078SPrabhakar Kushwaha unsigned int clock = (sw >> (6 - 2 * i)) & 3; 189*7d436078SPrabhakar Kushwaha switch (clock) { 190*7d436078SPrabhakar Kushwaha case 0: 191*7d436078SPrabhakar Kushwaha actual[i] = SRDS_PLLCR0_RFCK_SEL_100; 192*7d436078SPrabhakar Kushwaha break; 193*7d436078SPrabhakar Kushwaha case 1: 194*7d436078SPrabhakar Kushwaha actual[i] = SRDS_PLLCR0_RFCK_SEL_125; 195*7d436078SPrabhakar Kushwaha break; 196*7d436078SPrabhakar Kushwaha case 2: 197*7d436078SPrabhakar Kushwaha actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25; 198*7d436078SPrabhakar Kushwaha break; 199*7d436078SPrabhakar Kushwaha } 200*7d436078SPrabhakar Kushwaha } 201*7d436078SPrabhakar Kushwaha 202*7d436078SPrabhakar Kushwaha puts("SerDes1"); 203*7d436078SPrabhakar Kushwaha for (i = 0; i < NUM_SRDS_BANKS; i++) { 204*7d436078SPrabhakar Kushwaha u32 pllcr0 = srds_regs->bank[i].pllcr0; 205*7d436078SPrabhakar Kushwaha u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; 206*7d436078SPrabhakar Kushwaha if (expected != actual[i]) { 207*7d436078SPrabhakar Kushwaha printf("expects ref clk%d %sMHz, but actual is %sMHz\n", 208*7d436078SPrabhakar Kushwaha i + 1, serdes_clock_to_string(expected), 209*7d436078SPrabhakar Kushwaha serdes_clock_to_string(actual[i])); 210*7d436078SPrabhakar Kushwaha } 211*7d436078SPrabhakar Kushwaha } 212*7d436078SPrabhakar Kushwaha 213*7d436078SPrabhakar Kushwaha return 0; 214*7d436078SPrabhakar Kushwaha } 215*7d436078SPrabhakar Kushwaha 216*7d436078SPrabhakar Kushwaha void ft_board_setup(void *blob, bd_t *bd) 217*7d436078SPrabhakar Kushwaha { 218*7d436078SPrabhakar Kushwaha phys_addr_t base; 219*7d436078SPrabhakar Kushwaha phys_size_t size; 220*7d436078SPrabhakar Kushwaha 221*7d436078SPrabhakar Kushwaha ft_cpu_setup(blob, bd); 222*7d436078SPrabhakar Kushwaha 223*7d436078SPrabhakar Kushwaha base = getenv_bootm_low(); 224*7d436078SPrabhakar Kushwaha size = getenv_bootm_size(); 225*7d436078SPrabhakar Kushwaha 226*7d436078SPrabhakar Kushwaha fdt_fixup_memory(blob, (u64)base, (u64)size); 227*7d436078SPrabhakar Kushwaha 228*7d436078SPrabhakar Kushwaha #ifdef CONFIG_PCI 229*7d436078SPrabhakar Kushwaha pci_of_setup(blob, bd); 230*7d436078SPrabhakar Kushwaha #endif 231*7d436078SPrabhakar Kushwaha 232*7d436078SPrabhakar Kushwaha fdt_fixup_liodn(blob); 233*7d436078SPrabhakar Kushwaha 234*7d436078SPrabhakar Kushwaha #ifdef CONFIG_HAS_FSL_DR_USB 235*7d436078SPrabhakar Kushwaha fdt_fixup_dr_usb(blob, bd); 236*7d436078SPrabhakar Kushwaha #endif 237*7d436078SPrabhakar Kushwaha 238*7d436078SPrabhakar Kushwaha #ifdef CONFIG_SYS_DPAA_FMAN 239*7d436078SPrabhakar Kushwaha fdt_fixup_fman_ethernet(blob); 240*7d436078SPrabhakar Kushwaha #endif 241*7d436078SPrabhakar Kushwaha } 242*7d436078SPrabhakar Kushwaha 243*7d436078SPrabhakar Kushwaha void qixis_dump_switch(void) 244*7d436078SPrabhakar Kushwaha { 245*7d436078SPrabhakar Kushwaha int i, nr_of_cfgsw; 246*7d436078SPrabhakar Kushwaha 247*7d436078SPrabhakar Kushwaha QIXIS_WRITE(cms[0], 0x00); 248*7d436078SPrabhakar Kushwaha nr_of_cfgsw = QIXIS_READ(cms[1]); 249*7d436078SPrabhakar Kushwaha 250*7d436078SPrabhakar Kushwaha puts("DIP switch settings dump:\n"); 251*7d436078SPrabhakar Kushwaha for (i = 1; i <= nr_of_cfgsw; i++) { 252*7d436078SPrabhakar Kushwaha QIXIS_WRITE(cms[0], i); 253*7d436078SPrabhakar Kushwaha printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); 254*7d436078SPrabhakar Kushwaha } 255*7d436078SPrabhakar Kushwaha } 256