17d436078SPrabhakar Kushwaha /* 27d436078SPrabhakar Kushwaha * Copyright 2013 Freescale Semiconductor, Inc. 37d436078SPrabhakar Kushwaha * 47d436078SPrabhakar Kushwaha * SPDX-License-Identifier: GPL-2.0+ 57d436078SPrabhakar Kushwaha */ 67d436078SPrabhakar Kushwaha 77d436078SPrabhakar Kushwaha #include <common.h> 87d436078SPrabhakar Kushwaha #include <command.h> 97d436078SPrabhakar Kushwaha #include <i2c.h> 107d436078SPrabhakar Kushwaha #include <netdev.h> 117d436078SPrabhakar Kushwaha #include <linux/compiler.h> 127d436078SPrabhakar Kushwaha #include <asm/mmu.h> 137d436078SPrabhakar Kushwaha #include <asm/processor.h> 147d436078SPrabhakar Kushwaha #include <asm/cache.h> 157d436078SPrabhakar Kushwaha #include <asm/immap_85xx.h> 167d436078SPrabhakar Kushwaha #include <asm/fsl_law.h> 177d436078SPrabhakar Kushwaha #include <asm/fsl_serdes.h> 187d436078SPrabhakar Kushwaha #include <asm/fsl_portals.h> 197d436078SPrabhakar Kushwaha #include <asm/fsl_liodn.h> 207d436078SPrabhakar Kushwaha #include <fm_eth.h> 21*6259e291SZhao Qiang #include <hwconfig.h> 2248f6a9a2STang Yuantian #include <asm/mpc85xx_gpio.h> 237d436078SPrabhakar Kushwaha 247d436078SPrabhakar Kushwaha #include "../common/qixis.h" 257d436078SPrabhakar Kushwaha #include "t1040qds.h" 267d436078SPrabhakar Kushwaha #include "t1040qds_qixis.h" 277d436078SPrabhakar Kushwaha 287d436078SPrabhakar Kushwaha DECLARE_GLOBAL_DATA_PTR; 297d436078SPrabhakar Kushwaha 307d436078SPrabhakar Kushwaha int checkboard(void) 317d436078SPrabhakar Kushwaha { 327d436078SPrabhakar Kushwaha char buf[64]; 337d436078SPrabhakar Kushwaha u8 sw; 347d436078SPrabhakar Kushwaha struct cpu_type *cpu = gd->arch.cpu; 357d436078SPrabhakar Kushwaha static const char *const freq[] = {"100", "125", "156.25", "161.13", 367d436078SPrabhakar Kushwaha "122.88", "122.88", "122.88"}; 377d436078SPrabhakar Kushwaha int clock; 387d436078SPrabhakar Kushwaha 397d436078SPrabhakar Kushwaha printf("Board: %sQDS, ", cpu->name); 407d436078SPrabhakar Kushwaha printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ", 417d436078SPrabhakar Kushwaha QIXIS_READ(id), QIXIS_READ(arch)); 427d436078SPrabhakar Kushwaha 437d436078SPrabhakar Kushwaha sw = QIXIS_READ(brdcfg[0]); 447d436078SPrabhakar Kushwaha sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 457d436078SPrabhakar Kushwaha 467d436078SPrabhakar Kushwaha if (sw < 0x8) 477d436078SPrabhakar Kushwaha printf("vBank: %d\n", sw); 487d436078SPrabhakar Kushwaha else if (sw == 0x8) 497d436078SPrabhakar Kushwaha puts("PromJet\n"); 507d436078SPrabhakar Kushwaha else if (sw == 0x9) 517d436078SPrabhakar Kushwaha puts("NAND\n"); 527d436078SPrabhakar Kushwaha else if (sw == 0x15) 537d436078SPrabhakar Kushwaha printf("IFCCard\n"); 547d436078SPrabhakar Kushwaha else 557d436078SPrabhakar Kushwaha printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 567d436078SPrabhakar Kushwaha 577d436078SPrabhakar Kushwaha printf("FPGA: v%d (%s), build %d", 587d436078SPrabhakar Kushwaha (int)QIXIS_READ(scver), qixis_read_tag(buf), 597d436078SPrabhakar Kushwaha (int)qixis_read_minor()); 607d436078SPrabhakar Kushwaha /* the timestamp string contains "\n" at the end */ 617d436078SPrabhakar Kushwaha printf(" on %s", qixis_read_time(buf)); 627d436078SPrabhakar Kushwaha 637d436078SPrabhakar Kushwaha /* 647d436078SPrabhakar Kushwaha * Display the actual SERDES reference clocks as configured by the 657d436078SPrabhakar Kushwaha * dip switches on the board. Note that the SWx registers could 667d436078SPrabhakar Kushwaha * technically be set to force the reference clocks to match the 677d436078SPrabhakar Kushwaha * values that the SERDES expects (or vice versa). For now, however, 687d436078SPrabhakar Kushwaha * we just display both values and hope the user notices when they 697d436078SPrabhakar Kushwaha * don't match. 707d436078SPrabhakar Kushwaha */ 717d436078SPrabhakar Kushwaha puts("SERDES Reference: "); 727d436078SPrabhakar Kushwaha sw = QIXIS_READ(brdcfg[2]); 737d436078SPrabhakar Kushwaha clock = (sw >> 6) & 3; 747d436078SPrabhakar Kushwaha printf("Clock1=%sMHz ", freq[clock]); 757d436078SPrabhakar Kushwaha clock = (sw >> 4) & 3; 767d436078SPrabhakar Kushwaha printf("Clock2=%sMHz\n", freq[clock]); 777d436078SPrabhakar Kushwaha 787d436078SPrabhakar Kushwaha return 0; 797d436078SPrabhakar Kushwaha } 807d436078SPrabhakar Kushwaha 817d436078SPrabhakar Kushwaha int select_i2c_ch_pca9547(u8 ch) 827d436078SPrabhakar Kushwaha { 837d436078SPrabhakar Kushwaha int ret; 847d436078SPrabhakar Kushwaha 857d436078SPrabhakar Kushwaha ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); 867d436078SPrabhakar Kushwaha if (ret) { 877d436078SPrabhakar Kushwaha puts("PCA: failed to select proper channel\n"); 887d436078SPrabhakar Kushwaha return ret; 897d436078SPrabhakar Kushwaha } 907d436078SPrabhakar Kushwaha 917d436078SPrabhakar Kushwaha return 0; 927d436078SPrabhakar Kushwaha } 937d436078SPrabhakar Kushwaha 94*6259e291SZhao Qiang static void qe_board_setup(void) 95*6259e291SZhao Qiang { 96*6259e291SZhao Qiang u8 brdcfg15, brdcfg9; 97*6259e291SZhao Qiang 98*6259e291SZhao Qiang if (hwconfig("qe") && hwconfig("tdm")) { 99*6259e291SZhao Qiang brdcfg15 = QIXIS_READ(brdcfg[15]); 100*6259e291SZhao Qiang /* 101*6259e291SZhao Qiang * TDMRiser uses QE-TDM 102*6259e291SZhao Qiang * Route QE_TDM signals to TDM Riser slot 103*6259e291SZhao Qiang */ 104*6259e291SZhao Qiang QIXIS_WRITE(brdcfg[15], brdcfg15 | 7); 105*6259e291SZhao Qiang } else if (hwconfig("qe") && hwconfig("uart")) { 106*6259e291SZhao Qiang brdcfg15 = QIXIS_READ(brdcfg[15]); 107*6259e291SZhao Qiang brdcfg9 = QIXIS_READ(brdcfg[9]); 108*6259e291SZhao Qiang /* 109*6259e291SZhao Qiang * Route QE_TDM signals to UCC 110*6259e291SZhao Qiang * ProfiBus controlled by UCC3 111*6259e291SZhao Qiang */ 112*6259e291SZhao Qiang brdcfg15 &= 0xfc; 113*6259e291SZhao Qiang QIXIS_WRITE(brdcfg[15], brdcfg15 | 2); 114*6259e291SZhao Qiang QIXIS_WRITE(brdcfg[9], brdcfg9 | 4); 115*6259e291SZhao Qiang } 116*6259e291SZhao Qiang } 117*6259e291SZhao Qiang 1187d436078SPrabhakar Kushwaha int board_early_init_r(void) 1197d436078SPrabhakar Kushwaha { 1207d436078SPrabhakar Kushwaha #ifdef CONFIG_SYS_FLASH_BASE 1217d436078SPrabhakar Kushwaha const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 1227d436078SPrabhakar Kushwaha const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); 1237d436078SPrabhakar Kushwaha 1247d436078SPrabhakar Kushwaha /* 1257d436078SPrabhakar Kushwaha * Remap Boot flash + PROMJET region to caching-inhibited 1267d436078SPrabhakar Kushwaha * so that flash can be erased properly. 1277d436078SPrabhakar Kushwaha */ 1287d436078SPrabhakar Kushwaha 1297d436078SPrabhakar Kushwaha /* Flush d-cache and invalidate i-cache of any FLASH data */ 1307d436078SPrabhakar Kushwaha flush_dcache(); 1317d436078SPrabhakar Kushwaha invalidate_icache(); 1327d436078SPrabhakar Kushwaha 1337d436078SPrabhakar Kushwaha /* invalidate existing TLB entry for flash + promjet */ 1347d436078SPrabhakar Kushwaha disable_tlb(flash_esel); 1357d436078SPrabhakar Kushwaha 1367d436078SPrabhakar Kushwaha set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, 1377d436078SPrabhakar Kushwaha MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 1387d436078SPrabhakar Kushwaha 0, flash_esel, BOOKE_PAGESZ_256M, 1); 1397d436078SPrabhakar Kushwaha #endif 1407d436078SPrabhakar Kushwaha set_liodns(); 1417d436078SPrabhakar Kushwaha #ifdef CONFIG_SYS_DPAA_QBMAN 1427d436078SPrabhakar Kushwaha setup_portals(); 1437d436078SPrabhakar Kushwaha #endif 1447d436078SPrabhakar Kushwaha select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 1457d436078SPrabhakar Kushwaha 1467d436078SPrabhakar Kushwaha return 0; 1477d436078SPrabhakar Kushwaha } 1487d436078SPrabhakar Kushwaha 1497d436078SPrabhakar Kushwaha unsigned long get_board_sys_clk(void) 1507d436078SPrabhakar Kushwaha { 1517d436078SPrabhakar Kushwaha u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 1527d436078SPrabhakar Kushwaha 1537d436078SPrabhakar Kushwaha switch (sysclk_conf & 0x0F) { 1547d436078SPrabhakar Kushwaha case QIXIS_SYSCLK_64: 1557d436078SPrabhakar Kushwaha return 64000000; 1567d436078SPrabhakar Kushwaha case QIXIS_SYSCLK_83: 1577d436078SPrabhakar Kushwaha return 83333333; 1587d436078SPrabhakar Kushwaha case QIXIS_SYSCLK_100: 1597d436078SPrabhakar Kushwaha return 100000000; 1607d436078SPrabhakar Kushwaha case QIXIS_SYSCLK_125: 1617d436078SPrabhakar Kushwaha return 125000000; 1627d436078SPrabhakar Kushwaha case QIXIS_SYSCLK_133: 1637d436078SPrabhakar Kushwaha return 133333333; 1647d436078SPrabhakar Kushwaha case QIXIS_SYSCLK_150: 1657d436078SPrabhakar Kushwaha return 150000000; 1667d436078SPrabhakar Kushwaha case QIXIS_SYSCLK_160: 1677d436078SPrabhakar Kushwaha return 160000000; 1687d436078SPrabhakar Kushwaha case QIXIS_SYSCLK_166: 1697d436078SPrabhakar Kushwaha return 166666666; 1707d436078SPrabhakar Kushwaha } 1717d436078SPrabhakar Kushwaha return 66666666; 1727d436078SPrabhakar Kushwaha } 1737d436078SPrabhakar Kushwaha 1747d436078SPrabhakar Kushwaha unsigned long get_board_ddr_clk(void) 1757d436078SPrabhakar Kushwaha { 1767d436078SPrabhakar Kushwaha u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 1777d436078SPrabhakar Kushwaha 1787d436078SPrabhakar Kushwaha switch ((ddrclk_conf & 0x30) >> 4) { 1797d436078SPrabhakar Kushwaha case QIXIS_DDRCLK_100: 1807d436078SPrabhakar Kushwaha return 100000000; 1817d436078SPrabhakar Kushwaha case QIXIS_DDRCLK_125: 1827d436078SPrabhakar Kushwaha return 125000000; 1837d436078SPrabhakar Kushwaha case QIXIS_DDRCLK_133: 1847d436078SPrabhakar Kushwaha return 133333333; 1857d436078SPrabhakar Kushwaha } 1867d436078SPrabhakar Kushwaha return 66666666; 1877d436078SPrabhakar Kushwaha } 1887d436078SPrabhakar Kushwaha 1897d436078SPrabhakar Kushwaha #define NUM_SRDS_BANKS 2 1907d436078SPrabhakar Kushwaha int misc_init_r(void) 1917d436078SPrabhakar Kushwaha { 1927d436078SPrabhakar Kushwaha u8 sw; 1937d436078SPrabhakar Kushwaha serdes_corenet_t *srds_regs = 1947d436078SPrabhakar Kushwaha (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 1957d436078SPrabhakar Kushwaha u32 actual[NUM_SRDS_BANKS] = { 0 }; 1967d436078SPrabhakar Kushwaha int i; 1977d436078SPrabhakar Kushwaha 1987d436078SPrabhakar Kushwaha sw = QIXIS_READ(brdcfg[2]); 1997d436078SPrabhakar Kushwaha for (i = 0; i < NUM_SRDS_BANKS; i++) { 2007d436078SPrabhakar Kushwaha unsigned int clock = (sw >> (6 - 2 * i)) & 3; 2017d436078SPrabhakar Kushwaha switch (clock) { 2027d436078SPrabhakar Kushwaha case 0: 2037d436078SPrabhakar Kushwaha actual[i] = SRDS_PLLCR0_RFCK_SEL_100; 2047d436078SPrabhakar Kushwaha break; 2057d436078SPrabhakar Kushwaha case 1: 2067d436078SPrabhakar Kushwaha actual[i] = SRDS_PLLCR0_RFCK_SEL_125; 2077d436078SPrabhakar Kushwaha break; 2087d436078SPrabhakar Kushwaha case 2: 2097d436078SPrabhakar Kushwaha actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25; 2107d436078SPrabhakar Kushwaha break; 2117d436078SPrabhakar Kushwaha } 2127d436078SPrabhakar Kushwaha } 2137d436078SPrabhakar Kushwaha 2147d436078SPrabhakar Kushwaha puts("SerDes1"); 2157d436078SPrabhakar Kushwaha for (i = 0; i < NUM_SRDS_BANKS; i++) { 2167d436078SPrabhakar Kushwaha u32 pllcr0 = srds_regs->bank[i].pllcr0; 2177d436078SPrabhakar Kushwaha u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; 2187d436078SPrabhakar Kushwaha if (expected != actual[i]) { 2197d436078SPrabhakar Kushwaha printf("expects ref clk%d %sMHz, but actual is %sMHz\n", 2207d436078SPrabhakar Kushwaha i + 1, serdes_clock_to_string(expected), 2217d436078SPrabhakar Kushwaha serdes_clock_to_string(actual[i])); 2227d436078SPrabhakar Kushwaha } 2237d436078SPrabhakar Kushwaha } 2247d436078SPrabhakar Kushwaha 225*6259e291SZhao Qiang qe_board_setup(); 226*6259e291SZhao Qiang 2277d436078SPrabhakar Kushwaha return 0; 2287d436078SPrabhakar Kushwaha } 2297d436078SPrabhakar Kushwaha 2307d436078SPrabhakar Kushwaha void ft_board_setup(void *blob, bd_t *bd) 2317d436078SPrabhakar Kushwaha { 2327d436078SPrabhakar Kushwaha phys_addr_t base; 2337d436078SPrabhakar Kushwaha phys_size_t size; 2347d436078SPrabhakar Kushwaha 2357d436078SPrabhakar Kushwaha ft_cpu_setup(blob, bd); 2367d436078SPrabhakar Kushwaha 2377d436078SPrabhakar Kushwaha base = getenv_bootm_low(); 2387d436078SPrabhakar Kushwaha size = getenv_bootm_size(); 2397d436078SPrabhakar Kushwaha 2407d436078SPrabhakar Kushwaha fdt_fixup_memory(blob, (u64)base, (u64)size); 2417d436078SPrabhakar Kushwaha 2427d436078SPrabhakar Kushwaha #ifdef CONFIG_PCI 2437d436078SPrabhakar Kushwaha pci_of_setup(blob, bd); 2447d436078SPrabhakar Kushwaha #endif 2457d436078SPrabhakar Kushwaha 2467d436078SPrabhakar Kushwaha fdt_fixup_liodn(blob); 2477d436078SPrabhakar Kushwaha 2487d436078SPrabhakar Kushwaha #ifdef CONFIG_HAS_FSL_DR_USB 2497d436078SPrabhakar Kushwaha fdt_fixup_dr_usb(blob, bd); 2507d436078SPrabhakar Kushwaha #endif 2517d436078SPrabhakar Kushwaha 2527d436078SPrabhakar Kushwaha #ifdef CONFIG_SYS_DPAA_FMAN 2537d436078SPrabhakar Kushwaha fdt_fixup_fman_ethernet(blob); 2545b7672fcSPrabhakar Kushwaha fdt_fixup_board_enet(blob); 2557d436078SPrabhakar Kushwaha #endif 2567d436078SPrabhakar Kushwaha } 2577d436078SPrabhakar Kushwaha 2587d436078SPrabhakar Kushwaha void qixis_dump_switch(void) 2597d436078SPrabhakar Kushwaha { 2607d436078SPrabhakar Kushwaha int i, nr_of_cfgsw; 2617d436078SPrabhakar Kushwaha 2627d436078SPrabhakar Kushwaha QIXIS_WRITE(cms[0], 0x00); 2637d436078SPrabhakar Kushwaha nr_of_cfgsw = QIXIS_READ(cms[1]); 2647d436078SPrabhakar Kushwaha 2657d436078SPrabhakar Kushwaha puts("DIP switch settings dump:\n"); 2667d436078SPrabhakar Kushwaha for (i = 1; i <= nr_of_cfgsw; i++) { 2677d436078SPrabhakar Kushwaha QIXIS_WRITE(cms[0], i); 2687d436078SPrabhakar Kushwaha printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); 2697d436078SPrabhakar Kushwaha } 2707d436078SPrabhakar Kushwaha } 2718c618dd6SPrabhakar Kushwaha 2728c618dd6SPrabhakar Kushwaha int board_need_mem_reset(void) 2738c618dd6SPrabhakar Kushwaha { 2748c618dd6SPrabhakar Kushwaha return 1; 2758c618dd6SPrabhakar Kushwaha } 27648f6a9a2STang Yuantian 27748f6a9a2STang Yuantian #ifdef CONFIG_DEEP_SLEEP 27848f6a9a2STang Yuantian void board_mem_sleep_setup(void) 27948f6a9a2STang Yuantian { 28048f6a9a2STang Yuantian /* does not provide HW signals for power management */ 28148f6a9a2STang Yuantian QIXIS_WRITE(pwr_ctl[1], (QIXIS_READ(pwr_ctl[1]) & ~0x2)); 28248f6a9a2STang Yuantian /* Disable MCKE isolation */ 28348f6a9a2STang Yuantian gpio_set_value(2, 0); 28448f6a9a2STang Yuantian udelay(1); 28548f6a9a2STang Yuantian } 28648f6a9a2STang Yuantian #endif 287