1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * Author: Priyanka Jain <Priyanka.Jain@freescale.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <command.h> 10 #include <linux/ctype.h> 11 #include <asm/io.h> 12 #include <stdio_dev.h> 13 #include <video_fb.h> 14 #include <fsl_diu_fb.h> 15 #include "../common/qixis.h" 16 #include "../common/diu_ch7301.h" 17 #include "t1040qds.h" 18 #include "t1040qds_qixis.h" 19 20 /* 21 * DIU Area Descriptor 22 * 23 * Note that we need to byte-swap the value before it's written to the AD 24 * register. So even though the registers don't look like they're in the same 25 * bit positions as they are on the MPC8610, the same value is written to the 26 * AD register on the MPC8610 and on the P1022. 27 */ 28 #define AD_BYTE_F 0x10000000 29 #define AD_ALPHA_C_SHIFT 25 30 #define AD_BLUE_C_SHIFT 23 31 #define AD_GREEN_C_SHIFT 21 32 #define AD_RED_C_SHIFT 19 33 #define AD_PIXEL_S_SHIFT 16 34 #define AD_COMP_3_SHIFT 12 35 #define AD_COMP_2_SHIFT 8 36 #define AD_COMP_1_SHIFT 4 37 #define AD_COMP_0_SHIFT 0 38 39 void diu_set_pixel_clock(unsigned int pixclock) 40 { 41 unsigned long speed_ccb, temp; 42 u32 pixval; 43 int ret = 0; 44 speed_ccb = get_bus_freq(0); 45 temp = 1000000000 / pixclock; 46 temp *= 1000; 47 pixval = speed_ccb / temp; 48 49 /* Program HDMI encoder */ 50 /* Switch channel to DIU */ 51 select_i2c_ch_pca9547(I2C_MUX_CH_DIU); 52 53 /* Set dispaly encoder */ 54 ret = diu_set_dvi_encoder(temp); 55 if (ret) { 56 puts("Failed to set DVI encoder\n"); 57 return; 58 } 59 60 /* Switch channel to default */ 61 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 62 63 /* Program pixel clock */ 64 out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, 65 ((pixval << PXCK_BITS_START) & PXCK_MASK)); 66 /* enable clock*/ 67 out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, PXCKEN_MASK | 68 ((pixval << PXCK_BITS_START) & PXCK_MASK)); 69 } 70 71 int platform_diu_init(unsigned int xres, unsigned int yres, const char *port) 72 { 73 u32 pixel_format; 74 u8 sw; 75 76 /*Route I2C4 to DIU system as HSYNC/VSYNC*/ 77 sw = QIXIS_READ(brdcfg[5]); 78 QIXIS_WRITE(brdcfg[5], 79 ((sw & ~(BRDCFG5_IMX_MASK)) | (BRDCFG5_IMX_DIU))); 80 81 /*Configure Display ouput port as HDMI*/ 82 sw = QIXIS_READ(brdcfg[15]); 83 QIXIS_WRITE(brdcfg[15], 84 ((sw & ~(BRDCFG15_LCDPD_MASK | BRDCFG15_DIUSEL_MASK)) 85 | (BRDCFG15_LCDPD_ENABLED | BRDCFG15_DIUSEL_HDMI))); 86 87 pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) | 88 (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) | 89 (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) | 90 (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) | 91 (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT)); 92 93 printf("DIU: Switching to monitor @ %ux%u\n", xres, yres); 94 95 96 return fsl_diu_init(xres, yres, pixel_format, 0); 97 } 98