1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __DDR_H__ 8 #define __DDR_H__ 9 struct board_specific_parameters { 10 u32 n_ranks; 11 u32 datarate_mhz_high; 12 u32 rank_gb; 13 u32 clk_adjust; 14 u32 wrlvl_start; 15 u32 wrlvl_ctl_2; 16 u32 wrlvl_ctl_3; 17 u32 cpo; 18 u32 write_data_delay; 19 u32 force_2t; 20 }; 21 22 /* 23 * These tables contain all valid speeds we want to override with board 24 * specific parameters. datarate_mhz_high values need to be in ascending order 25 * for each n_ranks group. 26 */ 27 28 static const struct board_specific_parameters udimm0[] = { 29 /* 30 * memory controller 0 31 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T 32 * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | 33 */ 34 {2, 833, 4, 4, 6, 0x06060607, 0x08080807, 0xff, 2, 0}, 35 {2, 833, 0, 4, 6, 0x06060607, 0x08080807, 0xff, 2, 0}, 36 {2, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09, 0xff, 2, 0}, 37 {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09, 0xff, 2, 0}, 38 {2, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff, 2, 0}, 39 {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff, 2, 0}, 40 {1, 833, 4, 4, 6, 0x06060607, 0x08080807, 0xff, 2, 0}, 41 {1, 833, 0, 4, 6, 0x06060607, 0x08080807, 0xff, 2, 0}, 42 {1, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09, 0xff, 2, 0}, 43 {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09, 0xff, 2, 0}, 44 {1, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff, 2, 0}, 45 {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff, 2, 0}, 46 {} 47 }; 48 49 static const struct board_specific_parameters *udimms[] = { 50 udimm0, 51 }; 52 #endif 53