1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <command.h> 9 #include <i2c.h> 10 #include <netdev.h> 11 #include <linux/compiler.h> 12 #include <asm/mmu.h> 13 #include <asm/processor.h> 14 #include <asm/immap_85xx.h> 15 #include <asm/fsl_law.h> 16 #include <asm/fsl_serdes.h> 17 #include <asm/fsl_portals.h> 18 #include <asm/fsl_liodn.h> 19 #include <fm_eth.h> 20 #include "t102xrdb.h" 21 #include "cpld.h" 22 #include "../common/sleep.h" 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 int checkboard(void) 27 { 28 struct cpu_type *cpu = gd->arch.cpu; 29 static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"}; 30 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 31 u32 srds_s1; 32 33 srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL; 34 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; 35 36 printf("Board: %sRDB, ", cpu->name); 37 printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ", 38 CPLD_READ(hw_ver), CPLD_READ(sw_ver)); 39 40 #ifdef CONFIG_SDCARD 41 puts("SD/MMC\n"); 42 #elif CONFIG_SPIFLASH 43 puts("SPI\n"); 44 #else 45 u8 reg; 46 47 reg = CPLD_READ(flash_csr); 48 49 if (reg & CPLD_BOOT_SEL) { 50 puts("NAND\n"); 51 } else { 52 reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT); 53 printf("NOR vBank%d\n", reg); 54 } 55 #endif 56 57 puts("SERDES Reference Clocks:\n"); 58 if (srds_s1 == 0x95) 59 printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]); 60 else 61 printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[0], freq[0]); 62 63 return 0; 64 } 65 66 static void board_mux_lane(void) 67 { 68 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 69 u32 srds_prtcl_s1; 70 u8 reg = CPLD_READ(misc_ctl_status); 71 72 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & 73 FSL_CORENET2_RCWSR4_SRDS1_PRTCL; 74 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; 75 76 if (srds_prtcl_s1 == 0x95) { 77 /* Route Lane B to PCIE */ 78 CPLD_WRITE(misc_ctl_status, reg & ~CPLD_PCIE_SGMII_MUX); 79 } else { 80 /* Route Lane B to SGMII */ 81 CPLD_WRITE(misc_ctl_status, reg | CPLD_PCIE_SGMII_MUX); 82 } 83 CPLD_WRITE(boot_override, CPLD_OVERRIDE_MUX_EN); 84 } 85 86 int board_early_init_f(void) 87 { 88 #if defined(CONFIG_DEEP_SLEEP) 89 if (is_warm_boot()) 90 fsl_dp_disable_console(); 91 #endif 92 93 return 0; 94 } 95 96 int board_early_init_r(void) 97 { 98 #ifdef CONFIG_SYS_FLASH_BASE 99 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 100 int flash_esel = find_tlb_idx((void *)flashbase, 1); 101 /* 102 * Remap Boot flash region to caching-inhibited 103 * so that flash can be erased properly. 104 */ 105 106 /* Flush d-cache and invalidate i-cache of any FLASH data */ 107 flush_dcache(); 108 invalidate_icache(); 109 if (flash_esel == -1) { 110 /* very unlikely unless something is messed up */ 111 puts("Error: Could not find TLB for FLASH BASE\n"); 112 flash_esel = 2; /* give our best effort to continue */ 113 } else { 114 /* invalidate existing TLB entry for flash + promjet */ 115 disable_tlb(flash_esel); 116 } 117 118 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, 119 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 120 0, flash_esel, BOOKE_PAGESZ_256M, 1); 121 #endif 122 123 set_liodns(); 124 #ifdef CONFIG_SYS_DPAA_QBMAN 125 setup_portals(); 126 #endif 127 board_mux_lane(); 128 129 return 0; 130 } 131 132 unsigned long get_board_sys_clk(void) 133 { 134 return CONFIG_SYS_CLK_FREQ; 135 } 136 137 unsigned long get_board_ddr_clk(void) 138 { 139 return CONFIG_DDR_CLK_FREQ; 140 } 141 142 int misc_init_r(void) 143 { 144 return 0; 145 } 146 147 int ft_board_setup(void *blob, bd_t *bd) 148 { 149 phys_addr_t base; 150 phys_size_t size; 151 152 ft_cpu_setup(blob, bd); 153 154 base = getenv_bootm_low(); 155 size = getenv_bootm_size(); 156 157 fdt_fixup_memory(blob, (u64)base, (u64)size); 158 159 #ifdef CONFIG_PCI 160 pci_of_setup(blob, bd); 161 #endif 162 163 fdt_fixup_liodn(blob); 164 fdt_fixup_dr_usb(blob, bd); 165 166 #ifdef CONFIG_SYS_DPAA_FMAN 167 fdt_fixup_fman_ethernet(blob); 168 fdt_fixup_board_enet(blob); 169 #endif 170 171 return 0; 172 } 173