1 /*
2  * Copyright 2014 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <command.h>
9 #include <i2c.h>
10 #include <netdev.h>
11 #include <linux/compiler.h>
12 #include <asm/mmu.h>
13 #include <asm/processor.h>
14 #include <asm/immap_85xx.h>
15 #include <asm/fsl_law.h>
16 #include <asm/fsl_serdes.h>
17 #include <asm/fsl_portals.h>
18 #include <asm/fsl_liodn.h>
19 #include <asm/mpc85xx_gpio.h>
20 #include <fm_eth.h>
21 #include "t102xrdb.h"
22 #include "cpld.h"
23 
24 DECLARE_GLOBAL_DATA_PTR;
25 
26 int checkboard(void)
27 {
28 	struct cpu_type *cpu = gd->arch.cpu;
29 	static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
30 
31 	printf("Board: %sRDB, ", cpu->name);
32 	printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ",
33 	       CPLD_READ(hw_ver), CPLD_READ(sw_ver));
34 
35 #ifdef CONFIG_SDCARD
36 	puts("SD/MMC\n");
37 #elif CONFIG_SPIFLASH
38 	puts("SPI\n");
39 #else
40 	u8 reg;
41 
42 	reg = CPLD_READ(flash_csr);
43 
44 	if (reg & CPLD_BOOT_SEL) {
45 		puts("NAND\n");
46 	} else {
47 		reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
48 		printf("NOR vBank%d\n", reg);
49 	}
50 #endif
51 
52 	puts("SERDES Reference Clocks:\n");
53 	printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
54 
55 	return 0;
56 }
57 
58 int board_early_init_r(void)
59 {
60 #ifdef CONFIG_SYS_FLASH_BASE
61 	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
62 	int flash_esel = find_tlb_idx((void *)flashbase, 1);
63 	/*
64 	 * Remap Boot flash region to caching-inhibited
65 	 * so that flash can be erased properly.
66 	 */
67 
68 	/* Flush d-cache and invalidate i-cache of any FLASH data */
69 	flush_dcache();
70 	invalidate_icache();
71 	if (flash_esel == -1) {
72 		/* very unlikely unless something is messed up */
73 		puts("Error: Could not find TLB for FLASH BASE\n");
74 		flash_esel = 2;	/* give our best effort to continue */
75 	} else {
76 		/* invalidate existing TLB entry for flash + promjet */
77 		disable_tlb(flash_esel);
78 	}
79 
80 	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
81 		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
82 		0, flash_esel, BOOKE_PAGESZ_256M, 1);
83 #endif
84 
85 	set_liodns();
86 #ifdef CONFIG_SYS_DPAA_QBMAN
87 	setup_portals();
88 #endif
89 
90 	return 0;
91 }
92 
93 unsigned long get_board_sys_clk(void)
94 {
95 	return CONFIG_SYS_CLK_FREQ;
96 }
97 
98 unsigned long get_board_ddr_clk(void)
99 {
100 	return CONFIG_DDR_CLK_FREQ;
101 }
102 
103 int misc_init_r(void)
104 {
105 	return 0;
106 }
107 
108 int ft_board_setup(void *blob, bd_t *bd)
109 {
110 	phys_addr_t base;
111 	phys_size_t size;
112 
113 	ft_cpu_setup(blob, bd);
114 
115 	base = getenv_bootm_low();
116 	size = getenv_bootm_size();
117 
118 	fdt_fixup_memory(blob, (u64)base, (u64)size);
119 
120 #ifdef CONFIG_PCI
121 	pci_of_setup(blob, bd);
122 #endif
123 
124 	fdt_fixup_liodn(blob);
125 	fdt_fixup_dr_usb(blob, bd);
126 
127 #ifdef CONFIG_SYS_DPAA_FMAN
128 	fdt_fixup_fman_ethernet(blob);
129 	fdt_fixup_board_enet(blob);
130 #endif
131 
132 	return 0;
133 }
134 
135 #ifdef CONFIG_DEEP_SLEEP
136 void board_mem_sleep_setup(void)
137 {
138 	/* does not provide HW signals for power management */
139 	CPLD_WRITE(misc_ctl_status, (CPLD_READ(misc_ctl_status) & ~0x40));
140 	/* Disable MCKE isolation */
141 	gpio_set_value(2, 0);
142 	udelay(1);
143 }
144 #endif
145