xref: /openbmc/u-boot/board/freescale/t102xrdb/spl.c (revision 9ee16897)
1 /* Copyright 2014 Freescale Semiconductor, Inc.
2  *
3  * SPDX-License-Identifier:    GPL-2.0+
4  */
5 
6 #include <common.h>
7 #include <malloc.h>
8 #include <ns16550.h>
9 #include <nand.h>
10 #include <i2c.h>
11 #include <mmc.h>
12 #include <fsl_esdhc.h>
13 #include <spi_flash.h>
14 #include "../common/sleep.h"
15 
16 DECLARE_GLOBAL_DATA_PTR;
17 
18 phys_size_t get_effective_memsize(void)
19 {
20 	return CONFIG_SYS_L3_SIZE;
21 }
22 
23 unsigned long get_board_sys_clk(void)
24 {
25 	return CONFIG_SYS_CLK_FREQ;
26 }
27 
28 unsigned long get_board_ddr_clk(void)
29 {
30 	return CONFIG_DDR_CLK_FREQ;
31 }
32 
33 #if defined(CONFIG_SPL_MMC_BOOT)
34 #define GPIO1_SD_SEL 0x00020000
35 int board_mmc_getcd(struct mmc *mmc)
36 {
37 	ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
38 	u32 val = in_be32(&pgpio->gpdat);
39 
40 	/* GPIO1_14, 0: eMMC, 1: SD */
41 	val &= GPIO1_SD_SEL;
42 
43 	return val ? -1 : 1;
44 }
45 
46 int board_mmc_getwp(struct mmc *mmc)
47 {
48 	ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
49 	u32 val = in_be32(&pgpio->gpdat);
50 
51 	val &= GPIO1_SD_SEL;
52 
53 	return val ? -1 : 0;
54 }
55 #endif
56 
57 void board_init_f(ulong bootflag)
58 {
59 	u32 plat_ratio, sys_clk, ccb_clk;
60 	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
61 
62 	/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
63 	memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
64 
65 	/* Update GD pointer */
66 	gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
67 
68 	console_init_f();
69 
70 #ifdef CONFIG_DEEP_SLEEP
71 	/* disable the console if boot from deep sleep */
72 	if (is_warm_boot())
73 		fsl_dp_disable_console();
74 #endif
75 
76 	/* initialize selected port with appropriate baud rate */
77 	sys_clk = get_board_sys_clk();
78 	plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
79 	ccb_clk = sys_clk * plat_ratio / 2;
80 
81 	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
82 		     ccb_clk / 16 / CONFIG_BAUDRATE);
83 
84 #if defined(CONFIG_SPL_MMC_BOOT)
85 	puts("\nSD boot...\n");
86 #elif defined(CONFIG_SPL_SPI_BOOT)
87 	puts("\nSPI boot...\n");
88 #elif defined(CONFIG_SPL_NAND_BOOT)
89 	puts("\nNAND boot...\n");
90 #endif
91 
92 	relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
93 }
94 
95 void board_init_r(gd_t *gd, ulong dest_addr)
96 {
97 	bd_t *bd;
98 
99 	bd = (bd_t *)(gd + sizeof(gd_t));
100 	memset(bd, 0, sizeof(bd_t));
101 	gd->bd = bd;
102 	bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
103 	bd->bi_memsize = CONFIG_SYS_L3_SIZE;
104 
105 	probecpu();
106 	get_clocks();
107 	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
108 			CONFIG_SPL_RELOC_MALLOC_SIZE);
109 
110 #ifdef CONFIG_SPL_NAND_BOOT
111 	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
112 			    (uchar *)CONFIG_ENV_ADDR);
113 #endif
114 #ifdef CONFIG_SPL_MMC_BOOT
115 	mmc_initialize(bd);
116 	mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
117 			   (uchar *)CONFIG_ENV_ADDR);
118 #endif
119 #ifdef CONFIG_SPL_SPI_BOOT
120 	spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
121 			   (uchar *)CONFIG_ENV_ADDR);
122 #endif
123 
124 	gd->env_addr  = (ulong)(CONFIG_ENV_ADDR);
125 	gd->env_valid = 1;
126 
127 	i2c_init_all();
128 
129 	gd->ram_size = initdram(0);
130 
131 #ifdef CONFIG_SPL_MMC_BOOT
132 	mmc_boot();
133 #elif defined(CONFIG_SPL_SPI_BOOT)
134 	spi_boot();
135 #elif defined(CONFIG_SPL_NAND_BOOT)
136 	nand_boot();
137 #endif
138 }
139