1 /* Copyright 2014 Freescale Semiconductor, Inc. 2 * 3 * SPDX-License-Identifier: GPL-2.0+ 4 */ 5 6 #include <common.h> 7 #include <console.h> 8 #include <environment.h> 9 #include <malloc.h> 10 #include <ns16550.h> 11 #include <nand.h> 12 #include <i2c.h> 13 #include <mmc.h> 14 #include <fsl_esdhc.h> 15 #include <spi_flash.h> 16 #include "../common/sleep.h" 17 #include "../common/spl.h" 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 phys_size_t get_effective_memsize(void) 22 { 23 return CONFIG_SYS_L3_SIZE; 24 } 25 26 unsigned long get_board_sys_clk(void) 27 { 28 return CONFIG_SYS_CLK_FREQ; 29 } 30 31 unsigned long get_board_ddr_clk(void) 32 { 33 return CONFIG_DDR_CLK_FREQ; 34 } 35 36 #if defined(CONFIG_SPL_MMC_BOOT) 37 #define GPIO1_SD_SEL 0x00020000 38 int board_mmc_getcd(struct mmc *mmc) 39 { 40 ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); 41 u32 val = in_be32(&pgpio->gpdat); 42 43 /* GPIO1_14, 0: eMMC, 1: SD */ 44 val &= GPIO1_SD_SEL; 45 46 return val ? -1 : 1; 47 } 48 49 int board_mmc_getwp(struct mmc *mmc) 50 { 51 ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); 52 u32 val = in_be32(&pgpio->gpdat); 53 54 val &= GPIO1_SD_SEL; 55 56 return val ? -1 : 0; 57 } 58 #endif 59 60 void board_init_f(ulong bootflag) 61 { 62 u32 plat_ratio, sys_clk, ccb_clk; 63 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 64 65 /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ 66 memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); 67 68 /* Update GD pointer */ 69 gd = (gd_t *)(CONFIG_SPL_GD_ADDR); 70 71 console_init_f(); 72 73 #ifdef CONFIG_DEEP_SLEEP 74 /* disable the console if boot from deep sleep */ 75 if (is_warm_boot()) 76 fsl_dp_disable_console(); 77 #endif 78 79 /* initialize selected port with appropriate baud rate */ 80 sys_clk = get_board_sys_clk(); 81 plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; 82 ccb_clk = sys_clk * plat_ratio / 2; 83 84 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, 85 ccb_clk / 16 / CONFIG_BAUDRATE); 86 87 #if defined(CONFIG_SPL_MMC_BOOT) 88 puts("\nSD boot...\n"); 89 #elif defined(CONFIG_SPL_SPI_BOOT) 90 puts("\nSPI boot...\n"); 91 #elif defined(CONFIG_SPL_NAND_BOOT) 92 puts("\nNAND boot...\n"); 93 #endif 94 95 relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); 96 } 97 98 void board_init_r(gd_t *gd, ulong dest_addr) 99 { 100 bd_t *bd; 101 102 bd = (bd_t *)(gd + sizeof(gd_t)); 103 memset(bd, 0, sizeof(bd_t)); 104 gd->bd = bd; 105 bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; 106 bd->bi_memsize = CONFIG_SYS_L3_SIZE; 107 108 arch_cpu_init(); 109 get_clocks(); 110 mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, 111 CONFIG_SPL_RELOC_MALLOC_SIZE); 112 gd->flags |= GD_FLG_FULL_MALLOC_INIT; 113 114 #ifdef CONFIG_SPL_NAND_BOOT 115 nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, 116 (uchar *)CONFIG_ENV_ADDR); 117 #endif 118 #ifdef CONFIG_SPL_MMC_BOOT 119 mmc_initialize(bd); 120 mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, 121 (uchar *)CONFIG_ENV_ADDR); 122 #endif 123 #ifdef CONFIG_SPL_SPI_BOOT 124 fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, 125 (uchar *)CONFIG_ENV_ADDR); 126 #endif 127 128 gd->env_addr = (ulong)(CONFIG_ENV_ADDR); 129 gd->env_valid = ENV_VALID; 130 131 i2c_init_all(); 132 133 dram_init(); 134 135 #ifdef CONFIG_SPL_MMC_BOOT 136 mmc_boot(); 137 #elif defined(CONFIG_SPL_SPI_BOOT) 138 fsl_spi_boot(); 139 #elif defined(CONFIG_SPL_NAND_BOOT) 140 nand_boot(); 141 #endif 142 } 143