1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <command.h> 9 #include <netdev.h> 10 #include <asm/mmu.h> 11 #include <asm/processor.h> 12 #include <asm/immap_85xx.h> 13 #include <asm/fsl_law.h> 14 #include <asm/fsl_serdes.h> 15 #include <asm/fsl_portals.h> 16 #include <asm/fsl_liodn.h> 17 #include <malloc.h> 18 #include <fm_eth.h> 19 #include <fsl_mdio.h> 20 #include <miiphy.h> 21 #include <phy.h> 22 #include <asm/fsl_dtsec.h> 23 #include <asm/fsl_serdes.h> 24 25 int board_eth_init(bd_t *bis) 26 { 27 #if defined(CONFIG_FMAN_ENET) 28 int i, interface; 29 struct memac_mdio_info dtsec_mdio_info; 30 struct memac_mdio_info tgec_mdio_info; 31 struct mii_dev *dev; 32 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 33 u32 srds_s1; 34 35 srds_s1 = in_be32(&gur->rcwsr[4]) & 36 FSL_CORENET2_RCWSR4_SRDS1_PRTCL; 37 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; 38 39 dtsec_mdio_info.regs = 40 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; 41 42 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; 43 44 /* Register the 1G MDIO bus */ 45 fm_memac_mdio_init(bis, &dtsec_mdio_info); 46 47 tgec_mdio_info.regs = 48 (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; 49 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; 50 51 /* Register the 10G MDIO bus */ 52 fm_memac_mdio_init(bis, &tgec_mdio_info); 53 54 /* Set the two on-board RGMII PHY address */ 55 fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR); 56 fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR); 57 58 switch (srds_s1) { 59 case 0x95: 60 /* 10G XFI with Aquantia PHY */ 61 fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); 62 break; 63 default: 64 printf("SerDes protocol 0x%x is not supported on T102xRDB\n", 65 srds_s1); 66 break; 67 } 68 69 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { 70 interface = fm_info_get_enet_if(i); 71 switch (interface) { 72 case PHY_INTERFACE_MODE_RGMII: 73 dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); 74 fm_info_set_mdio(i, dev); 75 break; 76 default: 77 break; 78 } 79 } 80 81 for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { 82 switch (fm_info_get_enet_if(i)) { 83 case PHY_INTERFACE_MODE_XGMII: 84 dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); 85 fm_info_set_mdio(i, dev); 86 break; 87 default: 88 break; 89 } 90 } 91 92 cpu_eth_init(bis); 93 #endif /* CONFIG_FMAN_ENET */ 94 95 return pci_eth_init(bis); 96 } 97 98 void fdt_fixup_board_enet(void *fdt) 99 { 100 } 101