148c6f328SShengzhou Liu /* 248c6f328SShengzhou Liu * Copyright 2014 Freescale Semiconductor, Inc. 348c6f328SShengzhou Liu * 4e8a7f1c3SShengzhou Liu * Shengzhou Liu <Shengzhou.Liu@freescale.com> 5e8a7f1c3SShengzhou Liu * 648c6f328SShengzhou Liu * SPDX-License-Identifier: GPL-2.0+ 748c6f328SShengzhou Liu */ 848c6f328SShengzhou Liu 948c6f328SShengzhou Liu #include <common.h> 1048c6f328SShengzhou Liu #include <command.h> 1148c6f328SShengzhou Liu #include <netdev.h> 1248c6f328SShengzhou Liu #include <asm/mmu.h> 1348c6f328SShengzhou Liu #include <asm/processor.h> 1448c6f328SShengzhou Liu #include <asm/immap_85xx.h> 1548c6f328SShengzhou Liu #include <asm/fsl_law.h> 1648c6f328SShengzhou Liu #include <asm/fsl_serdes.h> 1748c6f328SShengzhou Liu #include <asm/fsl_portals.h> 1848c6f328SShengzhou Liu #include <asm/fsl_liodn.h> 1948c6f328SShengzhou Liu #include <malloc.h> 2048c6f328SShengzhou Liu #include <fm_eth.h> 2148c6f328SShengzhou Liu #include <fsl_mdio.h> 2248c6f328SShengzhou Liu #include <miiphy.h> 2348c6f328SShengzhou Liu #include <phy.h> 24*8225b2fdSShaohui Xie #include <fsl_dtsec.h> 2548c6f328SShengzhou Liu #include <asm/fsl_serdes.h> 26e26416a3SShengzhou Liu #include "../common/fman.h" 2748c6f328SShengzhou Liu 2848c6f328SShengzhou Liu int board_eth_init(bd_t *bis) 2948c6f328SShengzhou Liu { 3048c6f328SShengzhou Liu #if defined(CONFIG_FMAN_ENET) 3148c6f328SShengzhou Liu int i, interface; 3248c6f328SShengzhou Liu struct memac_mdio_info dtsec_mdio_info; 3348c6f328SShengzhou Liu struct memac_mdio_info tgec_mdio_info; 3448c6f328SShengzhou Liu struct mii_dev *dev; 3548c6f328SShengzhou Liu ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 3648c6f328SShengzhou Liu u32 srds_s1; 3748c6f328SShengzhou Liu 3848c6f328SShengzhou Liu srds_s1 = in_be32(&gur->rcwsr[4]) & 3948c6f328SShengzhou Liu FSL_CORENET2_RCWSR4_SRDS1_PRTCL; 4048c6f328SShengzhou Liu srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; 4148c6f328SShengzhou Liu 4248c6f328SShengzhou Liu dtsec_mdio_info.regs = 4348c6f328SShengzhou Liu (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; 4448c6f328SShengzhou Liu 4548c6f328SShengzhou Liu dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; 4648c6f328SShengzhou Liu 4748c6f328SShengzhou Liu /* Register the 1G MDIO bus */ 4848c6f328SShengzhou Liu fm_memac_mdio_init(bis, &dtsec_mdio_info); 4948c6f328SShengzhou Liu 5048c6f328SShengzhou Liu tgec_mdio_info.regs = 5148c6f328SShengzhou Liu (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; 5248c6f328SShengzhou Liu tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; 5348c6f328SShengzhou Liu 5448c6f328SShengzhou Liu /* Register the 10G MDIO bus */ 5548c6f328SShengzhou Liu fm_memac_mdio_init(bis, &tgec_mdio_info); 5648c6f328SShengzhou Liu 57e26416a3SShengzhou Liu /* Set the on-board RGMII PHY address */ 5848c6f328SShengzhou Liu fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR); 5948c6f328SShengzhou Liu 6048c6f328SShengzhou Liu switch (srds_s1) { 61e8a7f1c3SShengzhou Liu #ifdef CONFIG_T1024RDB 6248c6f328SShengzhou Liu case 0x95: 63e26416a3SShengzhou Liu /* set the on-board RGMII2 PHY */ 64e26416a3SShengzhou Liu fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR); 65e26416a3SShengzhou Liu 66e26416a3SShengzhou Liu /* set 10G XFI with Aquantia AQR105 PHY */ 6748c6f328SShengzhou Liu fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); 6848c6f328SShengzhou Liu break; 69e8a7f1c3SShengzhou Liu #endif 70e8a7f1c3SShengzhou Liu case 0x6a: 71e8a7f1c3SShengzhou Liu case 0x6b: 72e26416a3SShengzhou Liu case 0x77: 73e26416a3SShengzhou Liu case 0x135: 74e26416a3SShengzhou Liu /* set the on-board 2.5G SGMII AQR105 PHY */ 75e8a7f1c3SShengzhou Liu fm_info_set_phy_address(FM1_DTSEC3, SGMII_AQR_PHY_ADDR); 76e8a7f1c3SShengzhou Liu #ifdef CONFIG_T1023RDB 77e8a7f1c3SShengzhou Liu /* set the on-board 1G SGMII RTL8211F PHY */ 78e8a7f1c3SShengzhou Liu fm_info_set_phy_address(FM1_DTSEC1, SGMII_RTK_PHY_ADDR); 79e8a7f1c3SShengzhou Liu #endif 80e26416a3SShengzhou Liu break; 8148c6f328SShengzhou Liu default: 8248c6f328SShengzhou Liu printf("SerDes protocol 0x%x is not supported on T102xRDB\n", 8348c6f328SShengzhou Liu srds_s1); 8448c6f328SShengzhou Liu break; 8548c6f328SShengzhou Liu } 8648c6f328SShengzhou Liu 8748c6f328SShengzhou Liu for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { 8848c6f328SShengzhou Liu interface = fm_info_get_enet_if(i); 8948c6f328SShengzhou Liu switch (interface) { 9048c6f328SShengzhou Liu case PHY_INTERFACE_MODE_RGMII: 9148c6f328SShengzhou Liu dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); 9248c6f328SShengzhou Liu fm_info_set_mdio(i, dev); 9348c6f328SShengzhou Liu break; 94e8a7f1c3SShengzhou Liu case PHY_INTERFACE_MODE_SGMII: 95e8a7f1c3SShengzhou Liu #if defined(CONFIG_T1023RDB) 96e8a7f1c3SShengzhou Liu dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); 97e8a7f1c3SShengzhou Liu #elif defined(CONFIG_T1024RDB) 98e8a7f1c3SShengzhou Liu dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); 99e8a7f1c3SShengzhou Liu #endif 100e8a7f1c3SShengzhou Liu fm_info_set_mdio(i, dev); 101e8a7f1c3SShengzhou Liu break; 102e26416a3SShengzhou Liu case PHY_INTERFACE_MODE_SGMII_2500: 103e26416a3SShengzhou Liu dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); 104e26416a3SShengzhou Liu fm_info_set_mdio(i, dev); 105e26416a3SShengzhou Liu break; 10648c6f328SShengzhou Liu default: 10748c6f328SShengzhou Liu break; 10848c6f328SShengzhou Liu } 10948c6f328SShengzhou Liu } 11048c6f328SShengzhou Liu 11148c6f328SShengzhou Liu for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { 11248c6f328SShengzhou Liu switch (fm_info_get_enet_if(i)) { 11348c6f328SShengzhou Liu case PHY_INTERFACE_MODE_XGMII: 11448c6f328SShengzhou Liu dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); 11548c6f328SShengzhou Liu fm_info_set_mdio(i, dev); 11648c6f328SShengzhou Liu break; 11748c6f328SShengzhou Liu default: 11848c6f328SShengzhou Liu break; 11948c6f328SShengzhou Liu } 12048c6f328SShengzhou Liu } 12148c6f328SShengzhou Liu 12248c6f328SShengzhou Liu cpu_eth_init(bis); 12348c6f328SShengzhou Liu #endif /* CONFIG_FMAN_ENET */ 12448c6f328SShengzhou Liu 12548c6f328SShengzhou Liu return pci_eth_init(bis); 12648c6f328SShengzhou Liu } 12748c6f328SShengzhou Liu 128e26416a3SShengzhou Liu void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, 129e26416a3SShengzhou Liu enum fm_port port, int offset) 130e26416a3SShengzhou Liu { 131e8a7f1c3SShengzhou Liu #if defined(CONFIG_T1024RDB) 132e8a7f1c3SShengzhou Liu if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) || 133e8a7f1c3SShengzhou Liu (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) && 134e26416a3SShengzhou Liu (port == FM1_DTSEC3)) { 135e26416a3SShengzhou Liu fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4"); 136ea753267SShengzhou Liu fdt_setprop_string(fdt, offset, "phy-connection-type", 137ea753267SShengzhou Liu "sgmii-2500"); 138e26416a3SShengzhou Liu fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3"); 139e26416a3SShengzhou Liu } 140e8a7f1c3SShengzhou Liu #endif 141e26416a3SShengzhou Liu } 142e26416a3SShengzhou Liu 14348c6f328SShengzhou Liu void fdt_fixup_board_enet(void *fdt) 14448c6f328SShengzhou Liu { 14548c6f328SShengzhou Liu } 146