1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <i2c.h> 9 #include <hwconfig.h> 10 #include <asm/mmu.h> 11 #include <fsl_ddr_sdram.h> 12 #include <fsl_ddr_dimm_params.h> 13 #include <asm/fsl_law.h> 14 #include <asm/mpc85xx_gpio.h> 15 16 DECLARE_GLOBAL_DATA_PTR; 17 18 struct board_specific_parameters { 19 u32 n_ranks; 20 u32 datarate_mhz_high; 21 u32 rank_gb; 22 u32 clk_adjust; 23 u32 wrlvl_start; 24 u32 wrlvl_ctl_2; 25 u32 wrlvl_ctl_3; 26 }; 27 28 /* 29 * datarate_mhz_high values need to be in ascending order 30 */ 31 static const struct board_specific_parameters udimm0[] = { 32 /* 33 * memory controller 0 34 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | 35 * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | 36 */ 37 {2, 833, 0, 4, 6, 0x06060607, 0x08080807,}, 38 {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,}, 39 {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, 40 {1, 833, 0, 4, 6, 0x06060607, 0x08080807,}, 41 {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,}, 42 {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, 43 {} 44 }; 45 46 static const struct board_specific_parameters *udimms[] = { 47 udimm0, 48 }; 49 50 void fsl_ddr_board_options(memctl_options_t *popts, 51 dimm_params_t *pdimm, 52 unsigned int ctrl_num) 53 { 54 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; 55 ulong ddr_freq; 56 struct cpu_type *cpu = gd->arch.cpu; 57 58 if (ctrl_num > 1) { 59 printf("Not supported controller number %d\n", ctrl_num); 60 return; 61 } 62 if (!pdimm->n_ranks) 63 return; 64 65 pbsp = udimms[0]; 66 67 /* Get clk_adjust according to the board ddr freqency and n_banks 68 * specified in board_specific_parameters table. 69 */ 70 ddr_freq = get_ddr_freq(0) / 1000000; 71 while (pbsp->datarate_mhz_high) { 72 if (pbsp->n_ranks == pdimm->n_ranks && 73 (pdimm->rank_density >> 30) >= pbsp->rank_gb) { 74 if (ddr_freq <= pbsp->datarate_mhz_high) { 75 popts->clk_adjust = pbsp->clk_adjust; 76 popts->wrlvl_start = pbsp->wrlvl_start; 77 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; 78 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; 79 goto found; 80 } 81 pbsp_highest = pbsp; 82 } 83 pbsp++; 84 } 85 86 if (pbsp_highest) { 87 printf("Error: board specific timing not found\n"); 88 printf("for data rate %lu MT/s\n", ddr_freq); 89 printf("Trying to use the highest speed (%u) parameters\n", 90 pbsp_highest->datarate_mhz_high); 91 popts->clk_adjust = pbsp_highest->clk_adjust; 92 popts->wrlvl_start = pbsp_highest->wrlvl_start; 93 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; 94 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; 95 } else { 96 panic("DIMM is not supported by this board"); 97 } 98 found: 99 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", 100 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); 101 debug("\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, ", 102 pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2); 103 debug("wrlvl_ctrl_3 0x%x\n", pbsp->wrlvl_ctl_3); 104 105 /* 106 * Factors to consider for half-strength driver enable: 107 * - number of DIMMs installed 108 */ 109 popts->half_strength_driver_enable = 0; 110 /* 111 * Write leveling override 112 */ 113 popts->wrlvl_override = 1; 114 popts->wrlvl_sample = 0xf; 115 116 /* 117 * rtt and rtt_wr override 118 */ 119 popts->rtt_override = 0; 120 121 /* Enable ZQ calibration */ 122 popts->zq_en = 1; 123 124 /* DHC_EN =1, ODT = 75 Ohm */ 125 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_OFF); 126 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_OFF); 127 128 /* T1023 supports max DDR bus 32bit width, T1024 supports DDR 64bit, 129 * force DDR bus width to 32bit for T1023 130 */ 131 if (cpu->soc_ver == SVR_T1023) 132 popts->data_bus_width = DDR_DATA_BUS_WIDTH_32; 133 134 #ifdef CONFIG_FORCE_DDR_DATA_BUS_WIDTH_32 135 /* for DDR bus 32bit test on T1024 */ 136 popts->data_bus_width = DDR_DATA_BUS_WIDTH_32; 137 #endif 138 } 139 140 #if defined(CONFIG_DEEP_SLEEP) 141 void board_mem_sleep_setup(void) 142 { 143 void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE; 144 145 /* does not provide HW signals for power management */ 146 clrbits_8(cpld_base + 0x17, 0x40); 147 /* Disable MCKE isolation */ 148 gpio_set_value(2, 0); 149 udelay(1); 150 } 151 #endif 152 153 phys_size_t initdram(int board_type) 154 { 155 phys_size_t dram_size; 156 157 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) 158 puts("Initializing....using SPD\n"); 159 160 dram_size = fsl_ddr_sdram(); 161 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 162 dram_size *= 0x100000; 163 #else 164 /* DDR has been initialised by first stage boot loader */ 165 dram_size = fsl_ddr_sdram_size(); 166 #endif 167 168 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) 169 fsl_dp_resume(); 170 #endif 171 172 return dram_size; 173 } 174