1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <i2c.h> 9 #include <hwconfig.h> 10 #include <asm/mmu.h> 11 #include <fsl_ddr_sdram.h> 12 #include <fsl_ddr_dimm_params.h> 13 #include <asm/fsl_law.h> 14 15 DECLARE_GLOBAL_DATA_PTR; 16 17 struct board_specific_parameters { 18 u32 n_ranks; 19 u32 datarate_mhz_high; 20 u32 rank_gb; 21 u32 clk_adjust; 22 u32 wrlvl_start; 23 u32 wrlvl_ctl_2; 24 u32 wrlvl_ctl_3; 25 }; 26 27 /* 28 * datarate_mhz_high values need to be in ascending order 29 */ 30 static const struct board_specific_parameters udimm0[] = { 31 /* 32 * memory controller 0 33 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | 34 * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | 35 */ 36 {2, 833, 0, 4, 6, 0x06060607, 0x08080807,}, 37 {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,}, 38 {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, 39 {1, 833, 0, 4, 6, 0x06060607, 0x08080807,}, 40 {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,}, 41 {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, 42 {} 43 }; 44 45 static const struct board_specific_parameters *udimms[] = { 46 udimm0, 47 }; 48 49 void fsl_ddr_board_options(memctl_options_t *popts, 50 dimm_params_t *pdimm, 51 unsigned int ctrl_num) 52 { 53 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; 54 ulong ddr_freq; 55 struct cpu_type *cpu = gd->arch.cpu; 56 57 if (ctrl_num > 1) { 58 printf("Not supported controller number %d\n", ctrl_num); 59 return; 60 } 61 if (!pdimm->n_ranks) 62 return; 63 64 pbsp = udimms[0]; 65 66 /* Get clk_adjust according to the board ddr freqency and n_banks 67 * specified in board_specific_parameters table. 68 */ 69 ddr_freq = get_ddr_freq(0) / 1000000; 70 while (pbsp->datarate_mhz_high) { 71 if (pbsp->n_ranks == pdimm->n_ranks && 72 (pdimm->rank_density >> 30) >= pbsp->rank_gb) { 73 if (ddr_freq <= pbsp->datarate_mhz_high) { 74 popts->clk_adjust = pbsp->clk_adjust; 75 popts->wrlvl_start = pbsp->wrlvl_start; 76 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; 77 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; 78 goto found; 79 } 80 pbsp_highest = pbsp; 81 } 82 pbsp++; 83 } 84 85 if (pbsp_highest) { 86 printf("Error: board specific timing not found\n"); 87 printf("for data rate %lu MT/s\n", ddr_freq); 88 printf("Trying to use the highest speed (%u) parameters\n", 89 pbsp_highest->datarate_mhz_high); 90 popts->clk_adjust = pbsp_highest->clk_adjust; 91 popts->wrlvl_start = pbsp_highest->wrlvl_start; 92 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; 93 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; 94 } else { 95 panic("DIMM is not supported by this board"); 96 } 97 found: 98 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", 99 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); 100 debug("\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, ", 101 pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2); 102 debug("wrlvl_ctrl_3 0x%x\n", pbsp->wrlvl_ctl_3); 103 104 /* 105 * Factors to consider for half-strength driver enable: 106 * - number of DIMMs installed 107 */ 108 popts->half_strength_driver_enable = 0; 109 /* 110 * Write leveling override 111 */ 112 popts->wrlvl_override = 1; 113 popts->wrlvl_sample = 0xf; 114 115 /* 116 * rtt and rtt_wr override 117 */ 118 popts->rtt_override = 0; 119 120 /* Enable ZQ calibration */ 121 popts->zq_en = 1; 122 123 /* DHC_EN =1, ODT = 75 Ohm */ 124 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_OFF); 125 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_OFF); 126 127 /* T1023 supports max DDR bus 32bit width, T1024 supports DDR 64bit, 128 * force DDR bus width to 32bit for T1023 129 */ 130 if (cpu->soc_ver == SVR_T1023) 131 popts->data_bus_width = DDR_DATA_BUS_WIDTH_32; 132 133 #ifdef CONFIG_FORCE_DDR_DATA_BUS_WIDTH_32 134 /* for DDR bus 32bit test on T1024 */ 135 popts->data_bus_width = DDR_DATA_BUS_WIDTH_32; 136 #endif 137 } 138 139 phys_size_t initdram(int board_type) 140 { 141 phys_size_t dram_size; 142 143 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) 144 puts("Initializing....using SPD\n"); 145 146 dram_size = fsl_ddr_sdram(); 147 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 148 dram_size *= 0x100000; 149 #else 150 /* DDR has been initialised by first stage boot loader */ 151 dram_size = fsl_ddr_sdram_size(); 152 #endif 153 return dram_size; 154 } 155