1T1024 SoC Overview 2------------------ 3The T1024/T1023 dual core and T1014/T1013 single core QorIQ communication processor 4combines two or one 64-bit Power Architecture e5500 core respectively with high 5performance datapath acceleration logic, and network peripheral bus interfaces 6required for networking and telecommunications. This processor can be used in 7applications such as enterprise WLAN access points, routers, switches, firewall 8and other packet processing intensive small enterprise and branch office appliances, 9and general-purpose embedded computing. Its high level of integration offers 10significant performance benefits and greatly helps to simplify board design. 11 12 13The T1024 SoC includes the following function and features: 14- two e5500 cores, each with a private 256 KB L2 cache 15 - Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant) 16 - Three levels of instructions: User, supervisor, and hypervisor 17 - Independent boot and reset 18 - Secure boot capability 19- 256 KB shared L3 CoreNet platform cache (CPC) 20- Interconnect CoreNet platform 21 - CoreNet coherency manager supporting coherent and noncoherent transactions 22 with prioritization and bandwidth allocation amongst CoreNet endpoints 23 - 150 Gbps coherent read bandwidth 24- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support 25- Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: 26 - Packet parsing, classification, and distribution 27 - Queue management for scheduling, packet sequencing, and congestion management 28 - Cryptography Acceleration (SEC 5.x) 29 - IEEE 1588 support 30 - Hardware buffer management for buffer allocation and deallocation 31 - MACSEC on DPAA-based Ethernet ports 32- Ethernet interfaces 33 - Four 1 Gbps Ethernet controllers 34- Parallel Ethernet interfaces 35 - Two RGMII interfaces 36- High speed peripheral interfaces 37 - Three PCI Express 2.0 controllers/ports running at up to 5 GHz 38 - One SATA controller supporting 1.5 and 3.0 Gb/s operation 39 - One QSGMII interface 40 - Four SGMII interface supporting 1000 Mbps 41 - Three SGMII interfaces supporting up to 2500 Mbps 42 - 10GbE XFI or 10Base-KR interface 43- Additional peripheral interfaces 44 - Two USB 2.0 controllers with integrated PHY 45 - SD/eSDHC/eMMC 46 - eSPI controller 47 - Four I2C controllers 48 - Four UARTs 49 - Four GPIO controllers 50 - Integrated flash controller (IFC) 51 - LCD interface (DIU) with 12 bit dual data rate 52- Multicore programmable interrupt controller (PIC) 53- Two 8-channel DMA engines 54- Single source clocking implementation 55- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) 56- QUICC Engine block 57 - 32-bit RISC controller for flexible support of the communications peripherals 58 - Serial DMA channel for receive and transmit on all serial channels 59 - Two universal communication controllers, supporting TDM, HDLC, and UART 60 61T1023 Personality 62------------------ 63T1023 is a reduced personality of T1024 without QUICC Engine, DIU, and 64unavailable deep sleep. Rest of the blocks are almost same as T1024. 65Differences between T1024 and T1023 66Feature T1024 T1023 67QUICC Engine: yes no 68DIU: yes no 69Deep Sleep: yes no 70I2C controller: 4 3 71DDR: 64-bit 32-bit 72IFC: 32-bit 28-bit 73 74 75T1024RDB board Overview 76----------------------- 77 - Ethernet 78 - Two on-board 10M/100M/1G bps RGMII ethernet ports 79 - One on-board 10G bps Base-T port. 80 - DDR Memory 81 - Supports 64-bit 4GB DDR3L DIMM 82 - PCIe 83 - One on-board PCIe slot. 84 - Two on-board PCIe Mini-PCIe connectors. 85 - IFC/Local Bus 86 - NOR: 128MB 16-bit NOR Flash 87 - NAND: 1GB 8-bit NAND flash 88 - CPLD: for system controlling with programable header on-board 89 - USB 90 - Supports two USB 2.0 ports with integrated PHYs 91 - Two type A ports with 5V@1.5A per port. 92 - SDHC 93 - one SD connector supporting 1.8V/3.3V via J53. 94 - SPI 95 - On-board 64MB SPI flash 96 - Other 97 - Two Serial ports 98 - Four I2C ports 99 100 101T1023RDB board Overview 102----------------------- 103- T1023 SoC integrating two 64-bit e5500 cores up to 1.4GHz 104- CoreNet fabric supporting coherent and noncoherent transactions with 105 prioritization and bandwidth allocation 106- SDRAM memory: 2GB Micron MT40A512M8HX unbuffered 32-bit DDR4 w/o ECC 107- Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC 108- Ethernet interfaces: 109 - one 1G RGMII port on-board(RTL8211FS PHY) 110 - one 1G SGMII port on-board(RTL8211FS PHY) 111 - one 2.5G SGMII port on-board(AQR105 PHY) 112- PCIe: Two Mini-PCIe connectors on-board. 113- SerDes: 4 lanes up to 10.3125GHz 114- NOR: 128MB S29GL01GS110TFIV10 Spansion NOR Flash 115- NAND: 512MB S34MS04G200BFI000 Spansion NAND Flash 116- eSPI: 64MB S25FL512SAGMFI010 Spansion SPI flash. 117- USB: one Type-A USB 2.0 port with internal PHY 118- eSDHC: support SD/MMC and eMMC card 119- 256Kbit M24256 I2C EEPROM 120- RTC: Real-time clock DS1339U on I2C bus 121- UART: one serial port on-board with RJ45 connector 122- Debugging: JTAG/COP for T1023 debugging 123 124 125Memory map on T1024RDB 126---------------------- 127Start Address End Address Description Size 1280xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB 1290xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB 1300xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB 1310xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB 1320xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB 1330xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB 1340xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB 1350xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB 1360xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB 1370xF_0000_0000 0xF_003F_FFFF DCSR 4MB 1380xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB 1390xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB 1400xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB 1410x0_0000_0000 0x0_ffff_ffff DDR 4GB 142 143 144128MB NOR Flash Memory Layout 145----------------------------- 146Start Address End Address Definition Max size 1470xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB 1480xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB 1490xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB 1500xEFE00000 0xEFE3FFFF QE firmware (current bank) 256KB 1510xED300000 0xEFDFFFFF rootfs (alt bank) 44MB 1520xED000000 0xED2FFFFF Guest image #3 (alternate bank) 3MB 1530xECD00000 0xECFFFFFF Guest image #2 (alternate bank) 3MB 1540xECA00000 0xECCFFFFF Guest image #1 (alternate bank) 3MB 1550xEC900000 0xEC9FFFFF HV config device tree(alt bank) 1MB 1560xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB 1570xEC700000 0xEC7FFFFF HV.uImage (alternate bank) 1MB 1580xEC020000 0xEC6FFFFF Linux.uImage (alt bank) ~7MB 1590xEC000000 0xEC01FFFF RCW (alt bank) 128KB 1600xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB 1610xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB 1620xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB 1630xEBE00000 0xEBE3FFFF QE firmware (alt bank) 256KB 1640xE9300000 0xEBDFFFFF rootfs (current bank) 44MB 1650xE9000000 0xE92FFFFF Guest image #3 (current bank) 3MB 1660xE8D00000 0xE8FFFFFF Guest image #2 (current bank) 3MB 1670xE8A00000 0xE8CFFFFF Guest image #1 (current bank) 3MB 1680xE8900000 0xE89FFFFF HV config device tree(cur bank) 1MB 1690xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB 1700xE8700000 0xE87FFFFF HV.uImage (current bank) 1MB 1710xE8020000 0xE86FFFFF Linux.uImage (current bank) ~7MB 1720xE8000000 0xE801FFFF RCW (current bank) 128KB 173 174 175T1024/T1023 Clock frequency 176--------------------------- 177BIN Core DDR Platform FMan 178Bin1: 1400MHz 1600MT/s 400MHz 700MHz 179Bin2: 1200MHz 1600MT/s 400MHz 600MHz 180Bin3: 1000MHz 1600MT/s 400MHz 500MHz 181 182 183Software configurations and board settings 184------------------------------------------ 1851. NOR boot: 186 a. build NOR boot image 187 $ make T1024RDB_defconfig 188 $ make 189 b. program u-boot.bin image to NOR flash 190 => tftp 1000000 u-boot.bin 191 => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize 192 on T1024RDB: 193 set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot 194 on T1023RDB: 195 set SW1[1:8] = '00010110', SW2[1] = '0', SW3[4] = '0' for NOR boot 196 197 Switching between default bank0 and alternate bank4 on NOR flash 198 To change boot source to vbank4: 199 on T1024RDB: 200 via software: run command 'cpld reset altbank' in u-boot. 201 via DIP-switch: set SW3[5:7] = '100' 202 on T1023RDB: 203 via software: run command 'gpio vbank4' in u-boot. 204 via DIP-switch: set SW3[5:7] = '100' 205 206 To change boot source to vbank0: 207 on T1024RDB: 208 via software: run command 'cpld reset' in u-boot. 209 via DIP-Switch: set SW3[5:7] = '000' 210 on T1023RDB: 211 via software: run command 'gpio vbank0' in u-boot. 212 via DIP-switch: set SW3[5:7] = '000' 213 2142. NAND Boot: 215 a. build PBL image for NAND boot 216 $ make T1024RDB_NAND_defconfig 217 $ make 218 b. program u-boot-with-spl-pbl.bin to NAND flash 219 => tftp 1000000 u-boot-with-spl-pbl.bin 220 => nand erase 0 $filesize 221 => nand write 1000000 0 $filesize 222 set SW1[1:8] = '10001000', SW2[1] = '1', SW3[4] = '1' for NAND boot 223 2243. SPI Boot: 225 a. build PBL image for SPI boot 226 $ make T1024RDB_SPIFLASH_defconfig 227 $ make 228 b. program u-boot-with-spl-pbl.bin to SPI flash 229 => tftp 1000000 u-boot-with-spl-pbl.bin 230 => sf probe 0 231 => sf erase 0 100000 232 => sf write 1000000 0 $filesize 233 => tftp 1000000 fsl_fman_ucode_t1024_xx.bin 234 => sf erase 100000 100000 235 => sf write 1000000 110000 20000 236 set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot 237 2384. SD Boot: 239 a. build PBL image for SD boot 240 $ make T1024RDB_SDCARD_defconfig 241 $ make 242 b. program u-boot-with-spl-pbl.bin to SD/MMC card 243 => tftp 1000000 u-boot-with-spl-pbl.bin 244 => mmc write 1000000 8 0x800 245 => tftp 1000000 fsl_fman_ucode_t1024_xx.bin 246 => mmc write 1000000 0x820 80 247 set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot 248 249 2502-stage NAND/SPI/SD boot loader 251------------------------------- 252PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM. 253SPL further initializes DDR using SPD and environment variables 254and copy u-boot(768 KB) from NAND/SPI/SD device to DDR. 255Finally SPL transers control to u-boot for futher booting. 256 257SPL has following features: 258 - Executes within 256K 259 - No relocation required 260 261Run time view of SPL framework 262------------------------------------------------- 263|Area | Address | 264------------------------------------------------- 265|SecureBoot header | 0xFFFC0000 (32KB) | 266------------------------------------------------- 267|GD, BD | 0xFFFC8000 (4KB) | 268------------------------------------------------- 269|ENV | 0xFFFC9000 (8KB) | 270------------------------------------------------- 271|HEAP | 0xFFFCB000 (30KB) | 272------------------------------------------------- 273|STACK | 0xFFFD8000 (22KB) | 274------------------------------------------------- 275|U-boot SPL | 0xFFFD8000 (160KB) | 276------------------------------------------------- 277 278NAND Flash memory Map on T1024RDB 279------------------------------------------------------------- 280Start End Definition Size 2810x000000 0x0FFFFF u-boot 1MB(2 block) 2820x100000 0x17FFFF u-boot env 512KB(1 block) 2830x180000 0x1FFFFF FMAN Ucode 512KB(1 block) 2840x200000 0x27FFFF QE Firmware 512KB(1 block) 285 286 287NAND Flash memory Map on T1023RDB 288---------------------------------------------------- 289Start End Definition Size 2900x000000 0x0FFFFF u-boot 1MB 2910x100000 0x15FFFF u-boot env 8KB 2920x160000 0x17FFFF FMAN Ucode 128KB 293 294 295SD Card memory Map on T1024RDB 296---------------------------------------------------- 297Block #blocks Definition Size 2980x008 2048 u-boot img 1MB 2990x800 0016 u-boot env 8KB 3000x820 0256 FMAN Ucode 128KB 3010x920 0256 QE Firmware 128KB(only T1024RDB) 302 303 30464MB SPI Flash memory Map on T102xRDB 305---------------------------------------------------- 306Start End Definition Size 3070x000000 0x0FFFFF u-boot img 1MB 3080x100000 0x101FFF u-boot env 8KB 3090x110000 0x12FFFF FMAN Ucode 128KB 3100x130000 0x14FFFF QE Firmware 128KB(only T1024RDB) 3110x300000 0x3FFFFF device tree 128KB 3120x400000 0x9FFFFF Linux kernel 6MB 3130xa00000 0x3FFFFFF rootfs 54MB 314 315 316For more details, please refer to T1024RDB Reference Manual 317and Freescale QorIQ SDK Infocenter document. 318