1T1024 SoC Overview 2------------------ 3The T1024/T1023 dual core and T1014/T1013 single core QorIQ communication processor 4combines two or one 64-bit Power Architecture e5500 core respectively with high 5performance datapath acceleration logic, and network peripheral bus interfaces 6required for networking and telecommunications. This processor can be used in 7applications such as enterprise WLAN access points, routers, switches, firewall 8and other packet processing intensive small enterprise and branch office appliances, 9and general-purpose embedded computing. Its high level of integration offers 10significant performance benefits and greatly helps to simplify board design. 11 12 13The T1024 SoC includes the following function and features: 14- two e5500 cores, each with a private 256 KB L2 cache 15 - Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant) 16 - Three levels of instructions: User, supervisor, and hypervisor 17 - Independent boot and reset 18 - Secure boot capability 19- 256 KB shared L3 CoreNet platform cache (CPC) 20- Interconnect CoreNet platform 21 - CoreNet coherency manager supporting coherent and noncoherent transactions 22 with prioritization and bandwidth allocation amongst CoreNet endpoints 23 - 150 Gbps coherent read bandwidth 24- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support 25- Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: 26 - Packet parsing, classification, and distribution 27 - Queue management for scheduling, packet sequencing, and congestion management 28 - Cryptography Acceleration (SEC 5.x) 29 - IEEE 1588 support 30 - Hardware buffer management for buffer allocation and deallocation 31 - MACSEC on DPAA-based Ethernet ports 32- Ethernet interfaces 33 - Four 1 Gbps Ethernet controllers 34- Parallel Ethernet interfaces 35 - Two RGMII interfaces 36- High speed peripheral interfaces 37 - Three PCI Express 2.0 controllers/ports running at up to 5 GHz 38 - One SATA controller supporting 1.5 and 3.0 Gb/s operation 39 - One QSGMII interface 40 - Four SGMII interface supporting 1000 Mbps 41 - Three SGMII interfaces supporting up to 2500 Mbps 42 - 10GbE XFI or 10Base-KR interface 43- Additional peripheral interfaces 44 - Two USB 2.0 controllers with integrated PHY 45 - SD/eSDHC/eMMC 46 - eSPI controller 47 - Four I2C controllers 48 - Four UARTs 49 - Four GPIO controllers 50 - Integrated flash controller (IFC) 51 - LCD interface (DIU) with 12 bit dual data rate 52- Multicore programmable interrupt controller (PIC) 53- Two 8-channel DMA engines 54- Single source clocking implementation 55- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) 56- QUICC Engine block 57 - 32-bit RISC controller for flexible support of the communications peripherals 58 - Serial DMA channel for receive and transmit on all serial channels 59 - Two universal communication controllers, supporting TDM, HDLC, and UART 60 61T1023 Personality 62------------------ 63T1023 is a reduced personality of T1024 without QUICC Engine, DIU, and 64unavailable deep sleep. Rest of the blocks are almost same as T1024. 65Differences between T1024 and T1023 66Feature T1024 T1023 67QUICC Engine: yes no 68DIU: yes no 69Deep Sleep: yes no 70I2C controller: 4 3 71DDR: 64-bit 32-bit 72IFC: 32-bit 28-bit 73 74 75T1024RDB board Overview 76----------------------- 77 - Ethernet 78 - Two on-board 10M/100M/1G bps RGMII ethernet ports 79 - One on-board 10G bps Base-T port. 80 - DDR Memory 81 - Supports 64-bit 4GB DDR3L DIMM 82 - PCIe 83 - One on-board PCIe slot. 84 - Two on-board PCIe Mini-PCIe connectors. 85 - IFC/Local Bus 86 - NOR: 128MB 16-bit NOR Flash 87 - NAND: 1GB 8-bit NAND flash 88 - CPLD: for system controlling with programable header on-board 89 - USB 90 - Supports two USB 2.0 ports with integrated PHYs 91 - Two type A ports with 5V@1.5A per port. 92 - SDHC 93 - one SD connector supporting 1.8V/3.3V via J53. 94 - SPI 95 - On-board 64MB SPI flash 96 - Other 97 - Two Serial ports 98 - Four I2C ports 99 100 101Memory map on T1024RDB 102---------------------- 103Start Address End Address Description Size 1040xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB 1050xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB 1060xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB 1070xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB 1080xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB 1090xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB 1100xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB 1110xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB 1120xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB 1130xF_0000_0000 0xF_003F_FFFF DCSR 4MB 1140xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB 1150xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB 1160xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB 1170x0_0000_0000 0x0_ffff_ffff DDR 4GB 118 119 120128MB NOR Flash memory Map 121-------------------------- 122Start Address End Address Definition Max size 1230xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB 1240xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB 1250xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB 1260xEFE00000 0xEFE3FFFF QE firmware (current bank) 256KB 1270xED300000 0xEFEFFFFF rootfs (alt bank) 44MB 1280xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB 1290xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB 1300xEC000000 0xEC01FFFF RCW (alt bank) 128KB 1310xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB 1320xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB 1330xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB 1340xEBE00000 0xEBE3FFFF QE firmware (alt bank) 256KB 1350xE9300000 0xEBEFFFFF rootfs (current bank) 44MB 1360xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB 1370xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB 1380xE8000000 0xE801FFFF RCW (current bank) 128KB 139 140 141T1024 Clock frequency 142--------------------- 143BIN Core DDR Platform FMan 144Bin1: 1400MHz 1600MT/s 400MHz 700MHz 145Bin2: 1200MHz 1600MT/s 400MHz 600MHz 146Bin3: 1000MHz 1600MT/s 400MHz 500MHz 147 148 149Software configurations and board settings 150------------------------------------------ 1511. NOR boot: 152 a. build NOR boot image 153 $ make T1024RDB_defconfig 154 $ make 155 b. program u-boot.bin image to NOR flash 156 => tftp 1000000 u-boot.bin 157 => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize 158 set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot 159 160 Switching between default bank0 and alternate bank4 on NOR flash 161 To change boot source to vbank4: 162 via software: run command 'cpld reset altbank' in u-boot. 163 via DIP-switch: set SW3[5:7] = '100' 164 165 To change boot source to vbank0: 166 via software: run command 'cpld reset' in u-boot. 167 via DIP-Switch: set SW3[5:7] = '000' 168 1692. NAND Boot: 170 a. build PBL image for NAND boot 171 $ make T1024RDB_NAND_defconfig 172 $ make 173 b. program u-boot-with-spl-pbl.bin to NAND flash 174 => tftp 1000000 u-boot-with-spl-pbl.bin 175 => nand erase 0 $filesize 176 => nand write 1000000 0 $filesize 177 set SW1[1:8] = '10001000', SW2[1] = '1', SW3[4] = '1' for NAND boot 178 1793. SPI Boot: 180 a. build PBL image for SPI boot 181 $ make T1024RDB_SPIFLASH_defconfig 182 $ make 183 b. program u-boot-with-spl-pbl.bin to SPI flash 184 => tftp 1000000 u-boot-with-spl-pbl.bin 185 => sf probe 0 186 => sf erase 0 f0000 187 => sf write 1000000 0 $filesize 188 set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot 189 1904. SD Boot: 191 a. build PBL image for SD boot 192 $ make T1024RDB_SDCARD_defconfig 193 $ make 194 b. program u-boot-with-spl-pbl.bin to SD/MMC card 195 => tftp 1000000 u-boot-with-spl-pbl.bin 196 => mmc write 1000000 8 0x800 197 => tftp 1000000 fsl_fman_ucode_t1024_xx.bin 198 => mmc write 1000000 0x820 80 199 set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot 200 201 2022-stage NAND/SPI/SD boot loader 203------------------------------- 204PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM. 205SPL further initializes DDR using SPD and environment variables 206and copy u-boot(768 KB) from NAND/SPI/SD device to DDR. 207Finally SPL transers control to u-boot for futher booting. 208 209SPL has following features: 210 - Executes within 256K 211 - No relocation required 212 213Run time view of SPL framework 214------------------------------------------------- 215|Area | Address | 216------------------------------------------------- 217|SecureBoot header | 0xFFFC0000 (32KB) | 218------------------------------------------------- 219|GD, BD | 0xFFFC8000 (4KB) | 220------------------------------------------------- 221|ENV | 0xFFFC9000 (8KB) | 222------------------------------------------------- 223|HEAP | 0xFFFCB000 (30KB) | 224------------------------------------------------- 225|STACK | 0xFFFD8000 (22KB) | 226------------------------------------------------- 227|U-boot SPL | 0xFFFD8000 (160KB) | 228------------------------------------------------- 229 230NAND Flash memory Map on T1024RDB 231------------------------------------------------------------- 232Start End Definition Size 2330x000000 0x0FFFFF u-boot 1MB(2 block) 2340x100000 0x17FFFF u-boot env 512KB(1 block) 2350x180000 0x1FFFFF FMAN Ucode 512KB(1 block) 2360x200000 0x27FFFF QE Firmware 512KB(1 block) 237 238 239SD Card memory Map on T1024RDB 240---------------------------------------------------- 241Block #blocks Definition Size 2420x008 2048 u-boot img 1MB 2430x800 0016 u-boot env 8KB 2440x820 0256 FMAN Ucode 128KB 2450x920 0256 QE Firmware 128KB 246 247 248SPI Flash memory Map on T1024RDB 249---------------------------------------------------- 250Start End Definition Size 2510x000000 0x0FFFFF u-boot img 1MB 2520x100000 0x101FFF u-boot env 8KB 2530x110000 0x12FFFF FMAN Ucode 128KB 2540x130000 0x14FFFF QE Firmware 128KB 255 256 257For more details, please refer to T1024RDB Reference Manual and access 258website www.freescale.com and Freescale QorIQ SDK Infocenter document. 259