Name Date Size #Lines LOC

..07-Mar-2021-

KconfigH A D07-Mar-2021208 159

MAINTAINERSH A D07-Mar-2021515 1615

MakefileH A D07-Mar-2021318 1811

READMEH A D07-Mar-202112.1 KiB322287

cpld.cH A D07-Mar-20212.5 KiB10371

cpld.hH A D07-Mar-20211.8 KiB4934

ddr.cH A D07-Mar-20216.3 KiB255190

eth_t102xrdb.cH A D07-Mar-20213.7 KiB145114

law.cH A D07-Mar-2021880 3224

pci.cH A D07-Mar-2021380 2315

spl.cH A D07-Mar-20213 KiB142105

t1023_nand_rcw.cfgH A D07-Mar-2021288 98

t1023_sd_rcw.cfgH A D07-Mar-2021288 98

t1023_spi_rcw.cfgH A D07-Mar-2021288 98

t1024_nand_rcw.cfgH A D07-Mar-2021280 98

t1024_pbi.cfgH A D07-Mar-2021496 2726

t1024_sd_rcw.cfgH A D07-Mar-2021280 98

t1024_spi_rcw.cfgH A D07-Mar-2021280 98

t102xrdb.cH A D07-Mar-20217.3 KiB328265

t102xrdb.hH A D07-Mar-2021350 169

tlb.cH A D07-Mar-20214 KiB11786

README

1T1024 SoC Overview
2------------------
3The T1024/T1023 dual core and T1014/T1013 single core QorIQ communication processor
4combines two or one 64-bit Power Architecture e5500 core respectively with high
5performance datapath acceleration logic, and network peripheral bus interfaces
6required for networking and telecommunications. This processor can be used in
7applications such as enterprise WLAN access points, routers, switches, firewall
8and other packet processing intensive small enterprise and branch office appliances,
9and general-purpose embedded computing. Its high level of integration offers
10significant performance benefits and greatly helps to simplify board design.
11
12
13The T1024 SoC includes the following function and features:
14- two e5500 cores, each with a private 256 KB L2 cache
15  - Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant)
16  - Three levels of instructions: User, supervisor, and hypervisor
17  - Independent boot and reset
18  - Secure boot capability
19- 256 KB shared L3 CoreNet platform cache (CPC)
20- Interconnect CoreNet platform
21  - CoreNet coherency manager supporting coherent and noncoherent transactions
22    with prioritization and bandwidth allocation amongst CoreNet endpoints
23  - 150 Gbps coherent read bandwidth
24- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
25- Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions:
26  - Packet parsing, classification, and distribution
27  - Queue management for scheduling, packet sequencing, and congestion management
28  - Cryptography Acceleration (SEC 5.x)
29  - IEEE 1588 support
30  - Hardware buffer management for buffer allocation and deallocation
31  - MACSEC on DPAA-based Ethernet ports
32- Ethernet interfaces
33  - Four 1 Gbps Ethernet controllers
34- Parallel Ethernet interfaces
35  - Two RGMII interfaces
36- High speed peripheral interfaces
37  - Three PCI Express 2.0 controllers/ports running at up to 5 GHz
38  - One SATA controller supporting 1.5 and 3.0 Gb/s operation
39  - One QSGMII interface
40  - Four SGMII interface supporting 1000 Mbps
41  - Three SGMII interfaces supporting up to 2500 Mbps
42  - 10GbE XFI or 10Base-KR interface
43- Additional peripheral interfaces
44  - Two USB 2.0 controllers with integrated PHY
45  - SD/eSDHC/eMMC
46  - eSPI controller
47  - Four I2C controllers
48  - Four UARTs
49  - Four GPIO controllers
50  - Integrated flash controller (IFC)
51  - LCD interface (DIU) with 12 bit dual data rate
52- Multicore programmable interrupt controller (PIC)
53- Two 8-channel DMA engines
54- Single source clocking implementation
55- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
56- QUICC Engine block
57  - 32-bit RISC controller for flexible support of the communications peripherals
58  - Serial DMA channel for receive and transmit on all serial channels
59  - Two universal communication controllers, supporting TDM, HDLC, and UART
60
61T1023 Personality
62------------------
63T1023 is a reduced personality of T1024 without QUICC Engine, DIU, and
64unavailable deep sleep. Rest of the blocks are almost same as T1024.
65Differences between T1024 and T1023
66Feature		T1024  T1023
67QUICC Engine:	yes    no
68DIU:		yes    no
69Deep Sleep:	yes    no
70I2C controller: 4      3
71DDR:		64-bit 32-bit
72IFC:		32-bit 28-bit
73Package:	23x23  19x19
74
75
76T1024RDB board Overview
77-----------------------
78 - Ethernet
79     - Two on-board 10M/100M/1G bps RGMII ethernet ports
80     - One on-board 10G bps Base-T port.
81 - DDR Memory
82     - Supports 64-bit 4GB DDR3L DIMM
83 - PCIe
84     - One on-board PCIe slot.
85     - Two on-board PCIe Mini-PCIe connectors.
86 - IFC/Local Bus
87     - NOR:  128MB 16-bit NOR Flash
88     - NAND: 1GB 8-bit NAND flash
89     - CPLD: for system controlling with programable header on-board
90 - USB
91     - Supports two USB 2.0 ports with integrated PHYs
92     - Two type A ports with 5V@1.5A per port.
93 - SDHC
94     - one SD connector supporting 1.8V/3.3V via J53.
95 - SPI
96     -  On-board 64MB SPI flash
97 - Other
98     - Two Serial ports
99     - Four I2C ports
100
101
102T1023RDB board Overview
103-----------------------
104- T1023 SoC integrating two 64-bit e5500 cores up to 1.4GHz
105- CoreNet fabric supporting coherent and noncoherent transactions with
106  prioritization and bandwidth allocation
107- SDRAM memory: 2GB Micron MT40A512M8HX unbuffered 32-bit DDR4 w/o ECC
108- Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC
109- Ethernet interfaces:
110  - one 1G RGMII port on-board(RTL8211FS PHY)
111  - one 1G SGMII port on-board(RTL8211FS PHY)
112  - one 2.5G SGMII port on-board(AQR105 PHY)
113- PCIe: Two Mini-PCIe connectors on-board.
114- SerDes: 4 lanes up to 10.3125GHz
115- NOR:  128MB S29GL01GS110TFIV10 Spansion NOR Flash
116- NAND: 512MB S34MS04G200BFI000 Spansion NAND Flash
117- eSPI: 64MB S25FL512SAGMFI010 Spansion SPI flash.
118- USB: one Type-A USB 2.0 port with internal PHY
119- eSDHC: support SD/MMC and eMMC card
120- 256Kbit M24256 I2C EEPROM
121- RTC: Real-time clock DS1339U on I2C bus
122- UART: one serial port on-board with RJ45 connector
123- Debugging: JTAG/COP for T1023 debugging
124
125
126Memory map on T1024RDB
127----------------------
128Start Address  End Address      Description			Size
1290xF_FFDF_0000  0xF_FFDF_0FFF    IFC - CPLD			4KB
1300xF_FF80_0000  0xF_FF80_FFFF    IFC - NAND Flash		64KB
1310xF_FE00_0000  0xF_FEFF_FFFF    CCSRBAR				16MB
1320xF_F802_0000  0xF_F802_FFFF    PCI Express 3 I/O Space		64KB
1330xF_F801_0000  0xF_F801_FFFF    PCI Express 2 I/O Space		64KB
1340xF_F800_0000  0xF_F800_FFFF    PCI Express 1 I/O Space		64KB
1350xF_F600_0000  0xF_F7FF_FFFF    Queue manager software portal   32MB
1360xF_F400_0000  0xF_F5FF_FFFF    Buffer manager software portal  32MB
1370xF_E800_0000  0xF_EFFF_FFFF    IFC - NOR Flash			128MB
1380xF_0000_0000  0xF_003F_FFFF    DCSR				4MB
1390xC_2000_0000  0xC_2FFF_FFFF    PCI Express 3 Mem Space		256MB
1400xC_1000_0000  0xC_1FFF_FFFF    PCI Express 2 Mem Space		256MB
1410xC_0000_0000  0xC_0FFF_FFFF    PCI Express 1 Mem Space		256MB
1420x0_0000_0000  0x0_ffff_ffff    DDR				4GB
143
144
145128MB NOR Flash Memory Layout
146-----------------------------
147Start Address   End Address     Definition			Max size
1480xEFF40000      0xEFFFFFFF      U-Boot (current bank)		768KB
1490xEFF20000      0xEFF3FFFF      U-Boot env (current bank)	128KB
1500xEFF00000      0xEFF1FFFF      FMAN Ucode (current bank)	128KB
1510xEFE00000      0xEFE3FFFF      QE firmware (current bank)	256KB
1520xED300000      0xEFDFFFFF      rootfs (alt bank)		44MB
1530xED000000      0xED2FFFFF      Guest image #3 (alternate bank) 3MB
1540xECD00000      0xECFFFFFF      Guest image #2 (alternate bank) 3MB
1550xECA00000	0xECCFFFFF	Guest image #1 (alternate bank) 3MB
1560xEC900000	0xEC9FFFFF	HV config device tree(alt bank)	1MB
1570xEC800000      0xEC8FFFFF      Hardware device tree (alt bank) 1MB
1580xEC700000	0xEC7FFFFF	HV.uImage (alternate bank)	1MB
1590xEC020000      0xEC6FFFFF      Linux.uImage (alt bank)		~7MB
1600xEC000000      0xEC01FFFF      RCW (alt bank)			128KB
1610xEBF40000      0xEBFFFFFF      U-Boot (alt bank)		768KB
1620xEBF20000      0xEBF3FFFF      U-Boot env (alt bank)		128KB
1630xEBF00000      0xEBF1FFFF      FMAN ucode (alt bank)		128KB
1640xEBE00000      0xEBE3FFFF      QE firmware (alt bank)		256KB
1650xE9300000      0xEBDFFFFF      rootfs (current bank)		44MB
1660xE9000000      0xE92FFFFF      Guest image #3 (current bank)   3MB
1670xE8D00000      0xE8FFFFFF      Guest image #2 (current bank)   3MB
1680xE8A00000	0xE8CFFFFF	Guest image #1 (current bank)	3MB
1690xE8900000	0xE89FFFFF	HV config device tree(cur bank) 1MB
1700xE8800000      0xE88FFFFF      Hardware device tree (cur bank) 1MB
1710xE8700000	0xE87FFFFF	HV.uImage (current bank)	1MB
1720xE8020000      0xE86FFFFF      Linux.uImage (current bank)	~7MB
1730xE8000000      0xE801FFFF      RCW (current bank)		128KB
174
175
176T1024/T1023 Clock frequency
177---------------------------
178BIN   Core     DDR       Platform  FMan
179Bin1: 1400MHz  1600MT/s  400MHz    700MHz
180Bin2: 1200MHz  1600MT/s  400MHz    600MHz
181Bin3: 1000MHz  1600MT/s  400MHz    500MHz
182
183
184Software configurations and board settings
185------------------------------------------
1861. NOR boot:
187   a. build NOR boot image
188	$  make T1024RDB_defconfig
189	$  make
190   b. program u-boot.bin image to NOR flash
191	=> tftp 1000000 u-boot.bin
192	=> pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
193	on T1024RDB:
194	   set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot
195	on T1023RDB:
196	   set SW1[1:8] = '00010111', SW2[1] = '1', SW3[4] = '0' for NOR boot
197
198   Switching between default bank0 and alternate bank4 on NOR flash
199   To change boot source to vbank4:
200   on T1024RDB:
201	via software:   run command 'cpld reset altbank' in U-Boot.
202	via DIP-switch: set SW3[5:7] = '100'
203   on T1023RDB:
204	via software:   run command 'switch bank4' in U-Boot.
205	via DIP-switch: set SW3[5:7] = '100'
206
207   To change boot source to vbank0:
208   on T1024RDB:
209	via software:   run command 'cpld reset' in U-Boot.
210	via DIP-Switch: set SW3[5:7] = '000'
211   on T1023RDB:
212	via software:   run command 'switch bank0' in U-Boot.
213	via DIP-switch: set SW3[5:7] = '000'
214
2152. NAND Boot:
216   a. build PBL image for NAND boot
217	$ make T1024RDB_NAND_defconfig
218	$ make
219   b. program u-boot-with-spl-pbl.bin to NAND flash
220	=> tftp 1000000 u-boot-with-spl-pbl.bin
221	=> nand erase 0 $filesize
222	=> nand write 1000000 0 $filesize
223	set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot
224
2253. SPI Boot:
226   a. build PBL image for SPI boot
227	$ make T1024RDB_SPIFLASH_defconfig
228	$ make
229   b. program u-boot-with-spl-pbl.bin to SPI flash
230	=> tftp 1000000 u-boot-with-spl-pbl.bin
231	=> sf probe 0
232	=> sf erase 0 100000
233	=> sf write 1000000 0 $filesize
234	=> tftp 1000000 fsl_fman_ucode_t1024_xx.bin
235	=> sf erase 100000 100000
236	=> sf write 1000000 110000 20000
237	set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
238
2394. SD Boot:
240   a. build PBL image for SD boot
241	$ make T1024RDB_SDCARD_defconfig
242	$ make
243   b. program u-boot-with-spl-pbl.bin to SD/MMC card
244	=> tftp 1000000 u-boot-with-spl-pbl.bin
245	=> mmc write 1000000 8 0x7f0
246	=> tftp 1000000 fsl_fman_ucode_t1024_xx.bin
247	=> mmc write 1000000 0x820 80
248	set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
249
250   SW3[3] = '1' for SD card(or 'switch sd' by software)
251   SW3[3] = '0' for eMMC (or 'switch emmc' by software)
252
253
2542-stage NAND/SPI/SD boot loader
255-------------------------------
256PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
257SPL further initializes DDR using SPD and environment variables
258and copy U-Boot(768 KB) from NAND/SPI/SD device to DDR.
259Finally SPL transers control to U-Boot for futher booting.
260
261SPL has following features:
262 - Executes within 256K
263 - No relocation required
264
265Run time view of SPL framework
266-------------------------------------------------
267|Area		   | Address			|
268-------------------------------------------------
269|SecureBoot header | 0xFFFC0000 (32KB)		|
270-------------------------------------------------
271|GD, BD		   | 0xFFFC8000 (4KB)		|
272-------------------------------------------------
273|ENV		   | 0xFFFC9000 (8KB)		|
274-------------------------------------------------
275|HEAP		   | 0xFFFCB000 (30KB)		|
276-------------------------------------------------
277|STACK		   | 0xFFFD8000 (22KB)		|
278-------------------------------------------------
279|U-Boot SPL	   | 0xFFFD8000 (160KB)		|
280-------------------------------------------------
281
282NAND Flash memory Map on T1024RDB
283-------------------------------------------------------------
284Start		End		Definition	Size
2850x000000	0x0FFFFF	U-Boot		1MB(2 block)
2860x100000	0x17FFFF	U-Boot env	512KB(1 block)
2870x180000	0x1FFFFF	FMAN Ucode	512KB(1 block)
2880x200000	0x27FFFF	QE Firmware	512KB(1 block)
289
290
291NAND Flash memory Map on T1023RDB
292----------------------------------------------------
293Start		End		Definition	Size
2940x000000	0x0FFFFF	U-Boot		1MB
2950x100000	0x15FFFF	U-Boot env	8KB
2960x160000	0x17FFFF	FMAN Ucode	128KB
297
298
299SD Card memory Map on T102xRDB
300----------------------------------------------------
301Block		#blocks		Definition	Size
3020x008		2048		U-Boot img	1MB
3030x800		0016		U-Boot env	8KB
3040x820		0256		FMAN Ucode	128KB
3050x920		0256		QE Firmware	128KB(only T1024RDB)
306
307
30864MB SPI Flash memory Map on T102xRDB
309----------------------------------------------------
310Start		End		Definition	Size
3110x000000	0x0FFFFF	U-Boot img	1MB
3120x100000	0x101FFF	U-Boot env	8KB
3130x110000	0x12FFFF	FMAN Ucode	128KB
3140x130000	0x14FFFF	QE Firmware	128KB(only T1024RDB)
3150x300000	0x3FFFFF	device tree	128KB
3160x400000	0x9FFFFF	Linux kernel    6MB
3170xa00000	0x3FFFFFF	rootfs		54MB
318
319
320For more details, please refer to T1024RDB/T1023RDB User Guide
321and Freescale QorIQ SDK Infocenter document.
322