1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2014 Freescale Semiconductor, Inc.
4  */
5 
6 #include <common.h>
7 #include <command.h>
8 #include <i2c.h>
9 #include <netdev.h>
10 #include <linux/compiler.h>
11 #include <asm/mmu.h>
12 #include <asm/processor.h>
13 #include <asm/cache.h>
14 #include <asm/immap_85xx.h>
15 #include <asm/fsl_law.h>
16 #include <asm/fsl_serdes.h>
17 #include <asm/fsl_liodn.h>
18 #include <fm_eth.h>
19 #include <hwconfig.h>
20 #include "../common/qixis.h"
21 #include "t102xqds.h"
22 #include "t102xqds_qixis.h"
23 #include "../common/sleep.h"
24 
25 DECLARE_GLOBAL_DATA_PTR;
26 
27 int checkboard(void)
28 {
29 	char buf[64];
30 	struct cpu_type *cpu = gd->arch.cpu;
31 	static const char *const freq[] = {"100", "125", "156.25", "100.0"};
32 	int clock;
33 	u8 sw = QIXIS_READ(arch);
34 
35 	printf("Board: %sQDS, ", cpu->name);
36 	printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
37 	printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
38 
39 #ifdef CONFIG_SDCARD
40 	puts("SD/MMC\n");
41 #elif CONFIG_SPIFLASH
42 	puts("SPI\n");
43 #else
44 	sw = QIXIS_READ(brdcfg[0]);
45 	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
46 
47 	if (sw < 0x8)
48 		printf("vBank: %d\n", sw);
49 	else if (sw == 0x8)
50 		puts("PromJet\n");
51 	else if (sw == 0x9)
52 		puts("NAND\n");
53 	else if (sw == 0x15)
54 		printf("IFC Card\n");
55 	else
56 		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
57 #endif
58 
59 	printf("FPGA: v%d (%s), build %d",
60 	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
61 	       (int)qixis_read_minor());
62 	/* the timestamp string contains "\n" at the end */
63 	printf(" on %s", qixis_read_time(buf));
64 
65 	puts("SERDES Reference: ");
66 	sw = QIXIS_READ(brdcfg[2]);
67 	clock = (sw >> 6) & 3;
68 	printf("Clock1=%sMHz ", freq[clock]);
69 	clock = (sw >> 4) & 3;
70 	printf("Clock2=%sMHz\n", freq[clock]);
71 
72 	return 0;
73 }
74 
75 int select_i2c_ch_pca9547(u8 ch)
76 {
77 	int ret;
78 
79 	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
80 	if (ret) {
81 		puts("PCA: failed to select proper channel\n");
82 		return ret;
83 	}
84 
85 	return 0;
86 }
87 
88 static int board_mux_lane_to_slot(void)
89 {
90 	ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
91 	u32 srds_prtcl_s1;
92 	u8 brdcfg9;
93 
94 	srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
95 				FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
96 	srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
97 
98 
99 	brdcfg9 = QIXIS_READ(brdcfg[9]);
100 	QIXIS_WRITE(brdcfg[9], brdcfg9 | BRDCFG9_XFI_TX_DISABLE);
101 
102 	switch (srds_prtcl_s1) {
103 	case 0:
104 		/* SerDes1 is not enabled */
105 		break;
106 	case 0xd5:
107 	case 0x5b:
108 	case 0x6b:
109 	case 0x77:
110 	case 0x6f:
111 	case 0x7f:
112 		QIXIS_WRITE(brdcfg[12], 0x8c);
113 		break;
114 	case 0x40:
115 		QIXIS_WRITE(brdcfg[12], 0xfc);
116 		break;
117 	case 0xd6:
118 	case 0x5a:
119 	case 0x6a:
120 	case 0x56:
121 		QIXIS_WRITE(brdcfg[12], 0x88);
122 		break;
123 	case 0x47:
124 		QIXIS_WRITE(brdcfg[12], 0xcc);
125 		break;
126 	case 0x46:
127 		QIXIS_WRITE(brdcfg[12], 0xc8);
128 		break;
129 	case 0x95:
130 	case 0x99:
131 		brdcfg9 &= ~BRDCFG9_XFI_TX_DISABLE;
132 		QIXIS_WRITE(brdcfg[9], brdcfg9);
133 		QIXIS_WRITE(brdcfg[12], 0x8c);
134 		break;
135 	case 0x116:
136 		QIXIS_WRITE(brdcfg[12], 0x00);
137 		break;
138 	case 0x115:
139 	case 0x119:
140 	case 0x129:
141 	case 0x12b:
142 		/* Aurora, PCIe, SGMII, SATA */
143 		QIXIS_WRITE(brdcfg[12], 0x04);
144 		break;
145 	default:
146 		printf("WARNING: unsupported for SerDes Protocol %d\n",
147 		       srds_prtcl_s1);
148 		return -1;
149 	}
150 
151 	return 0;
152 }
153 
154 #ifdef CONFIG_ARCH_T1024
155 static void board_mux_setup(void)
156 {
157 	u8 brdcfg15;
158 
159 	brdcfg15 = QIXIS_READ(brdcfg[15]);
160 	brdcfg15 &= ~BRDCFG15_DIUSEL_MASK;
161 
162 	if (hwconfig_arg_cmp("pin_mux", "tdm")) {
163 		/* Route QE_TDM multiplexed signals to TDM Riser slot */
164 		QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_TDM);
165 		QIXIS_WRITE(brdcfg[13], BRDCFG13_TDM_INTERFACE << 2);
166 		QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) &
167 			    ~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_TDM);
168 	} else if (hwconfig_arg_cmp("pin_mux", "ucc")) {
169 		/* to UCC (ProfiBus) interface */
170 		QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_UCC);
171 	} else if (hwconfig_arg_cmp("pin_mux", "hdmi")) {
172 		/* to DVI (HDMI) encoder */
173 		QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_HDMI);
174 	} else if (hwconfig_arg_cmp("pin_mux", "lcd")) {
175 		/* to DFP (LCD) encoder */
176 		QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_LCDFM |
177 			    BRDCFG15_LCDPD | BRDCFG15_DIUSEL_LCD);
178 	}
179 
180 	if (hwconfig_arg_cmp("adaptor", "sdxc"))
181 		/* Route SPI_CS multiplexed signals to SD slot */
182 		QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) &
183 			    ~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_SDHC);
184 }
185 #endif
186 
187 void board_retimer_ds125df111_init(void)
188 {
189 	u8 reg;
190 
191 	/* Retimer DS125DF111 is connected to I2C1_CH7_CH5 */
192 	reg = I2C_MUX_CH7;
193 	i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &reg, 1);
194 	reg = I2C_MUX_CH5;
195 	i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &reg, 1);
196 
197 	/* Access to Control/Shared register */
198 	reg = 0x0;
199 	i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
200 
201 	/* Read device revision and ID */
202 	i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
203 	debug("Retimer version id = 0x%x\n", reg);
204 
205 	/* Enable Broadcast */
206 	reg = 0x0c;
207 	i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
208 
209 	/* Reset Channel Registers */
210 	i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
211 	reg |= 0x4;
212 	i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
213 
214 	/* Enable override divider select and Enable Override Output Mux */
215 	i2c_read(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
216 	reg |= 0x24;
217 	i2c_write(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
218 
219 	/* Select VCO Divider to full rate (000) */
220 	i2c_read(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
221 	reg &= 0x8f;
222 	i2c_write(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
223 
224 	/* Select active PFD MUX input as re-timed data (001) */
225 	i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
226 	reg &= 0x3f;
227 	reg |= 0x20;
228 	i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
229 
230 	/* Set data rate as 10.3125 Gbps */
231 	reg = 0x0;
232 	i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
233 	reg = 0xb2;
234 	i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
235 	reg = 0x90;
236 	i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
237 	reg = 0xb3;
238 	i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
239 	reg = 0xcd;
240 	i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
241 }
242 
243 int board_early_init_f(void)
244 {
245 #if defined(CONFIG_DEEP_SLEEP)
246 	if (is_warm_boot())
247 		fsl_dp_disable_console();
248 #endif
249 
250 	return 0;
251 }
252 
253 int board_early_init_r(void)
254 {
255 #ifdef CONFIG_SYS_FLASH_BASE
256 	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
257 	int flash_esel = find_tlb_idx((void *)flashbase, 1);
258 
259 	/*
260 	 * Remap Boot flash + PROMJET region to caching-inhibited
261 	 * so that flash can be erased properly.
262 	 */
263 
264 	/* Flush d-cache and invalidate i-cache of any FLASH data */
265 	flush_dcache();
266 	invalidate_icache();
267 
268 	if (flash_esel == -1) {
269 		/* very unlikely unless something is messed up */
270 		puts("Error: Could not find TLB for FLASH BASE\n");
271 		flash_esel = 2; /* give our best effort to continue */
272 	} else {
273 		/* invalidate existing TLB entry for flash + promjet */
274 		disable_tlb(flash_esel);
275 	}
276 
277 	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
278 		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
279 		0, flash_esel, BOOKE_PAGESZ_256M, 1);
280 #endif
281 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
282 	board_mux_lane_to_slot();
283 	board_retimer_ds125df111_init();
284 
285 	/* Increase IO drive strength to address FCS error on RGMII */
286 	out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR, 0xbfdb7800);
287 
288 	return 0;
289 }
290 
291 unsigned long get_board_sys_clk(void)
292 {
293 	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
294 
295 	switch (sysclk_conf & 0x0F) {
296 	case QIXIS_SYSCLK_64:
297 		return 64000000;
298 	case QIXIS_SYSCLK_83:
299 		return 83333333;
300 	case QIXIS_SYSCLK_100:
301 		return 100000000;
302 	case QIXIS_SYSCLK_125:
303 		return 125000000;
304 	case QIXIS_SYSCLK_133:
305 		return 133333333;
306 	case QIXIS_SYSCLK_150:
307 		return 150000000;
308 	case QIXIS_SYSCLK_160:
309 		return 160000000;
310 	case QIXIS_SYSCLK_166:
311 		return 166666666;
312 	}
313 	return 66666666;
314 }
315 
316 unsigned long get_board_ddr_clk(void)
317 {
318 	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
319 
320 	switch ((ddrclk_conf & 0x30) >> 4) {
321 	case QIXIS_DDRCLK_100:
322 		return 100000000;
323 	case QIXIS_DDRCLK_125:
324 		return 125000000;
325 	case QIXIS_DDRCLK_133:
326 		return 133333333;
327 	}
328 	return 66666666;
329 }
330 
331 #define NUM_SRDS_PLL	2
332 int misc_init_r(void)
333 {
334 #ifdef CONFIG_ARCH_T1024
335 	board_mux_setup();
336 #endif
337 	return 0;
338 }
339 
340 void fdt_fixup_spi_mux(void *blob)
341 {
342 	int nodeoff = 0;
343 
344 	if (hwconfig_arg_cmp("pin_mux", "tdm")) {
345 		while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
346 			"eon,en25s64")) >= 0) {
347 			fdt_del_node(blob, nodeoff);
348 		}
349 	} else {
350 		/* remove tdm node */
351 		while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
352 			"maxim,ds26522")) >= 0) {
353 			fdt_del_node(blob, nodeoff);
354 		}
355 	}
356 }
357 
358 int ft_board_setup(void *blob, bd_t *bd)
359 {
360 	phys_addr_t base;
361 	phys_size_t size;
362 
363 	ft_cpu_setup(blob, bd);
364 
365 	base = env_get_bootm_low();
366 	size = env_get_bootm_size();
367 
368 	fdt_fixup_memory(blob, (u64)base, (u64)size);
369 
370 #ifdef CONFIG_PCI
371 	pci_of_setup(blob, bd);
372 #endif
373 
374 	fdt_fixup_liodn(blob);
375 
376 #ifdef CONFIG_HAS_FSL_DR_USB
377 	fsl_fdt_fixup_dr_usb(blob, bd);
378 #endif
379 
380 #ifdef CONFIG_SYS_DPAA_FMAN
381 	fdt_fixup_fman_ethernet(blob);
382 	fdt_fixup_board_enet(blob);
383 #endif
384 	fdt_fixup_spi_mux(blob);
385 
386 	return 0;
387 }
388 
389 void qixis_dump_switch(void)
390 {
391 	int i, nr_of_cfgsw;
392 
393 	QIXIS_WRITE(cms[0], 0x00);
394 	nr_of_cfgsw = QIXIS_READ(cms[1]);
395 
396 	puts("DIP switch settings dump:\n");
397 	for (i = 1; i <= nr_of_cfgsw; i++) {
398 		QIXIS_WRITE(cms[0], i);
399 		printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
400 	}
401 }
402