1*aba80048SShengzhou Liu /* 2*aba80048SShengzhou Liu * Copyright 2014 Freescale Semiconductor, Inc. 3*aba80048SShengzhou Liu * 4*aba80048SShengzhou Liu * SPDX-License-Identifier: GPL-2.0+ 5*aba80048SShengzhou Liu */ 6*aba80048SShengzhou Liu 7*aba80048SShengzhou Liu #include <common.h> 8*aba80048SShengzhou Liu #include <command.h> 9*aba80048SShengzhou Liu #include <i2c.h> 10*aba80048SShengzhou Liu #include <netdev.h> 11*aba80048SShengzhou Liu #include <linux/compiler.h> 12*aba80048SShengzhou Liu #include <asm/mmu.h> 13*aba80048SShengzhou Liu #include <asm/processor.h> 14*aba80048SShengzhou Liu #include <asm/cache.h> 15*aba80048SShengzhou Liu #include <asm/immap_85xx.h> 16*aba80048SShengzhou Liu #include <asm/fsl_law.h> 17*aba80048SShengzhou Liu #include <asm/fsl_serdes.h> 18*aba80048SShengzhou Liu #include <asm/fsl_portals.h> 19*aba80048SShengzhou Liu #include <asm/fsl_liodn.h> 20*aba80048SShengzhou Liu #include <fm_eth.h> 21*aba80048SShengzhou Liu #include <hwconfig.h> 22*aba80048SShengzhou Liu #include <asm/mpc85xx_gpio.h> 23*aba80048SShengzhou Liu #include "../common/qixis.h" 24*aba80048SShengzhou Liu #include "t102xqds.h" 25*aba80048SShengzhou Liu #include "t102xqds_qixis.h" 26*aba80048SShengzhou Liu 27*aba80048SShengzhou Liu DECLARE_GLOBAL_DATA_PTR; 28*aba80048SShengzhou Liu 29*aba80048SShengzhou Liu int checkboard(void) 30*aba80048SShengzhou Liu { 31*aba80048SShengzhou Liu char buf[64]; 32*aba80048SShengzhou Liu struct cpu_type *cpu = gd->arch.cpu; 33*aba80048SShengzhou Liu static const char *const freq[] = {"100", "125", "156.25", "100.0"}; 34*aba80048SShengzhou Liu int clock; 35*aba80048SShengzhou Liu u8 sw = QIXIS_READ(arch); 36*aba80048SShengzhou Liu 37*aba80048SShengzhou Liu printf("Board: %sQDS, ", cpu->name); 38*aba80048SShengzhou Liu printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4); 39*aba80048SShengzhou Liu printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1); 40*aba80048SShengzhou Liu 41*aba80048SShengzhou Liu #ifdef CONFIG_SDCARD 42*aba80048SShengzhou Liu puts("SD/MMC\n"); 43*aba80048SShengzhou Liu #elif CONFIG_SPIFLASH 44*aba80048SShengzhou Liu puts("SPI\n"); 45*aba80048SShengzhou Liu #else 46*aba80048SShengzhou Liu sw = QIXIS_READ(brdcfg[0]); 47*aba80048SShengzhou Liu sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 48*aba80048SShengzhou Liu 49*aba80048SShengzhou Liu if (sw < 0x8) 50*aba80048SShengzhou Liu printf("vBank: %d\n", sw); 51*aba80048SShengzhou Liu else if (sw == 0x8) 52*aba80048SShengzhou Liu puts("PromJet\n"); 53*aba80048SShengzhou Liu else if (sw == 0x9) 54*aba80048SShengzhou Liu puts("NAND\n"); 55*aba80048SShengzhou Liu else if (sw == 0x15) 56*aba80048SShengzhou Liu printf("IFC Card\n"); 57*aba80048SShengzhou Liu else 58*aba80048SShengzhou Liu printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 59*aba80048SShengzhou Liu #endif 60*aba80048SShengzhou Liu 61*aba80048SShengzhou Liu printf("FPGA: v%d (%s), build %d", 62*aba80048SShengzhou Liu (int)QIXIS_READ(scver), qixis_read_tag(buf), 63*aba80048SShengzhou Liu (int)qixis_read_minor()); 64*aba80048SShengzhou Liu /* the timestamp string contains "\n" at the end */ 65*aba80048SShengzhou Liu printf(" on %s", qixis_read_time(buf)); 66*aba80048SShengzhou Liu 67*aba80048SShengzhou Liu puts("SERDES Reference: "); 68*aba80048SShengzhou Liu sw = QIXIS_READ(brdcfg[2]); 69*aba80048SShengzhou Liu clock = (sw >> 6) & 3; 70*aba80048SShengzhou Liu printf("Clock1=%sMHz ", freq[clock]); 71*aba80048SShengzhou Liu clock = (sw >> 4) & 3; 72*aba80048SShengzhou Liu printf("Clock2=%sMHz\n", freq[clock]); 73*aba80048SShengzhou Liu 74*aba80048SShengzhou Liu return 0; 75*aba80048SShengzhou Liu } 76*aba80048SShengzhou Liu 77*aba80048SShengzhou Liu int select_i2c_ch_pca9547(u8 ch) 78*aba80048SShengzhou Liu { 79*aba80048SShengzhou Liu int ret; 80*aba80048SShengzhou Liu 81*aba80048SShengzhou Liu ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); 82*aba80048SShengzhou Liu if (ret) { 83*aba80048SShengzhou Liu puts("PCA: failed to select proper channel\n"); 84*aba80048SShengzhou Liu return ret; 85*aba80048SShengzhou Liu } 86*aba80048SShengzhou Liu 87*aba80048SShengzhou Liu return 0; 88*aba80048SShengzhou Liu } 89*aba80048SShengzhou Liu 90*aba80048SShengzhou Liu static int board_mux_lane_to_slot(void) 91*aba80048SShengzhou Liu { 92*aba80048SShengzhou Liu ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 93*aba80048SShengzhou Liu u32 srds_prtcl_s1; 94*aba80048SShengzhou Liu u8 brdcfg9; 95*aba80048SShengzhou Liu 96*aba80048SShengzhou Liu srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & 97*aba80048SShengzhou Liu FSL_CORENET2_RCWSR4_SRDS1_PRTCL; 98*aba80048SShengzhou Liu srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; 99*aba80048SShengzhou Liu 100*aba80048SShengzhou Liu 101*aba80048SShengzhou Liu brdcfg9 = QIXIS_READ(brdcfg[9]); 102*aba80048SShengzhou Liu QIXIS_WRITE(brdcfg[9], brdcfg9 | BRDCFG9_XFI_TX_DISABLE); 103*aba80048SShengzhou Liu 104*aba80048SShengzhou Liu switch (srds_prtcl_s1) { 105*aba80048SShengzhou Liu case 0: 106*aba80048SShengzhou Liu /* SerDes1 is not enabled */ 107*aba80048SShengzhou Liu break; 108*aba80048SShengzhou Liu case 0xd5: 109*aba80048SShengzhou Liu case 0x5b: 110*aba80048SShengzhou Liu case 0x6b: 111*aba80048SShengzhou Liu case 0x77: 112*aba80048SShengzhou Liu case 0x6f: 113*aba80048SShengzhou Liu case 0x7f: 114*aba80048SShengzhou Liu QIXIS_WRITE(brdcfg[12], 0x8c); 115*aba80048SShengzhou Liu break; 116*aba80048SShengzhou Liu case 0x40: 117*aba80048SShengzhou Liu QIXIS_WRITE(brdcfg[12], 0xfc); 118*aba80048SShengzhou Liu break; 119*aba80048SShengzhou Liu case 0xd6: 120*aba80048SShengzhou Liu case 0x5a: 121*aba80048SShengzhou Liu case 0x6a: 122*aba80048SShengzhou Liu case 0x56: 123*aba80048SShengzhou Liu QIXIS_WRITE(brdcfg[12], 0x88); 124*aba80048SShengzhou Liu break; 125*aba80048SShengzhou Liu case 0x47: 126*aba80048SShengzhou Liu QIXIS_WRITE(brdcfg[12], 0xcc); 127*aba80048SShengzhou Liu break; 128*aba80048SShengzhou Liu case 0x46: 129*aba80048SShengzhou Liu QIXIS_WRITE(brdcfg[12], 0xc8); 130*aba80048SShengzhou Liu break; 131*aba80048SShengzhou Liu case 0x95: 132*aba80048SShengzhou Liu case 0x99: 133*aba80048SShengzhou Liu brdcfg9 &= ~BRDCFG9_XFI_TX_DISABLE; 134*aba80048SShengzhou Liu QIXIS_WRITE(brdcfg[9], brdcfg9); 135*aba80048SShengzhou Liu QIXIS_WRITE(brdcfg[12], 0x8c); 136*aba80048SShengzhou Liu break; 137*aba80048SShengzhou Liu case 0x116: 138*aba80048SShengzhou Liu QIXIS_WRITE(brdcfg[12], 0x00); 139*aba80048SShengzhou Liu break; 140*aba80048SShengzhou Liu case 0x115: 141*aba80048SShengzhou Liu case 0x119: 142*aba80048SShengzhou Liu case 0x129: 143*aba80048SShengzhou Liu case 0x12b: 144*aba80048SShengzhou Liu /* Aurora, PCIe, SGMII, SATA */ 145*aba80048SShengzhou Liu QIXIS_WRITE(brdcfg[12], 0x04); 146*aba80048SShengzhou Liu break; 147*aba80048SShengzhou Liu default: 148*aba80048SShengzhou Liu printf("WARNING: unsupported for SerDes Protocol %d\n", 149*aba80048SShengzhou Liu srds_prtcl_s1); 150*aba80048SShengzhou Liu return -1; 151*aba80048SShengzhou Liu } 152*aba80048SShengzhou Liu 153*aba80048SShengzhou Liu return 0; 154*aba80048SShengzhou Liu } 155*aba80048SShengzhou Liu 156*aba80048SShengzhou Liu #ifdef CONFIG_PPC_T1024 157*aba80048SShengzhou Liu static void board_mux_setup(void) 158*aba80048SShengzhou Liu { 159*aba80048SShengzhou Liu u8 brdcfg15; 160*aba80048SShengzhou Liu 161*aba80048SShengzhou Liu brdcfg15 = QIXIS_READ(brdcfg[15]); 162*aba80048SShengzhou Liu brdcfg15 &= ~BRDCFG15_DIUSEL_MASK; 163*aba80048SShengzhou Liu 164*aba80048SShengzhou Liu if (hwconfig_arg_cmp("pin_mux", "tdm")) { 165*aba80048SShengzhou Liu /* Route QE_TDM multiplexed signals to TDM Riser slot */ 166*aba80048SShengzhou Liu QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_TDM); 167*aba80048SShengzhou Liu QIXIS_WRITE(brdcfg[13], BRDCFG13_TDM_INTERFACE << 2); 168*aba80048SShengzhou Liu } else if (hwconfig_arg_cmp("pin_mux", "ucc")) { 169*aba80048SShengzhou Liu /* to UCC (ProfiBus) interface */ 170*aba80048SShengzhou Liu QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_UCC); 171*aba80048SShengzhou Liu } else if (hwconfig_arg_cmp("pin_mux", "hdmi")) { 172*aba80048SShengzhou Liu /* to DVI (HDMI) encoder */ 173*aba80048SShengzhou Liu QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_HDMI); 174*aba80048SShengzhou Liu } else if (hwconfig_arg_cmp("pin_mux", "lcd")) { 175*aba80048SShengzhou Liu /* to DFP (LCD) encoder */ 176*aba80048SShengzhou Liu QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_LCDFM | 177*aba80048SShengzhou Liu BRDCFG15_LCDPD | BRDCFG15_DIUSEL_LCD); 178*aba80048SShengzhou Liu } 179*aba80048SShengzhou Liu } 180*aba80048SShengzhou Liu #endif 181*aba80048SShengzhou Liu 182*aba80048SShengzhou Liu int board_early_init_r(void) 183*aba80048SShengzhou Liu { 184*aba80048SShengzhou Liu #ifdef CONFIG_SYS_FLASH_BASE 185*aba80048SShengzhou Liu const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 186*aba80048SShengzhou Liu int flash_esel = find_tlb_idx((void *)flashbase, 1); 187*aba80048SShengzhou Liu 188*aba80048SShengzhou Liu /* 189*aba80048SShengzhou Liu * Remap Boot flash + PROMJET region to caching-inhibited 190*aba80048SShengzhou Liu * so that flash can be erased properly. 191*aba80048SShengzhou Liu */ 192*aba80048SShengzhou Liu 193*aba80048SShengzhou Liu /* Flush d-cache and invalidate i-cache of any FLASH data */ 194*aba80048SShengzhou Liu flush_dcache(); 195*aba80048SShengzhou Liu invalidate_icache(); 196*aba80048SShengzhou Liu 197*aba80048SShengzhou Liu if (flash_esel == -1) { 198*aba80048SShengzhou Liu /* very unlikely unless something is messed up */ 199*aba80048SShengzhou Liu puts("Error: Could not find TLB for FLASH BASE\n"); 200*aba80048SShengzhou Liu flash_esel = 2; /* give our best effort to continue */ 201*aba80048SShengzhou Liu } else { 202*aba80048SShengzhou Liu /* invalidate existing TLB entry for flash + promjet */ 203*aba80048SShengzhou Liu disable_tlb(flash_esel); 204*aba80048SShengzhou Liu } 205*aba80048SShengzhou Liu 206*aba80048SShengzhou Liu set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, 207*aba80048SShengzhou Liu MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 208*aba80048SShengzhou Liu 0, flash_esel, BOOKE_PAGESZ_256M, 1); 209*aba80048SShengzhou Liu #endif 210*aba80048SShengzhou Liu set_liodns(); 211*aba80048SShengzhou Liu #ifdef CONFIG_SYS_DPAA_QBMAN 212*aba80048SShengzhou Liu setup_portals(); 213*aba80048SShengzhou Liu #endif 214*aba80048SShengzhou Liu select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 215*aba80048SShengzhou Liu board_mux_lane_to_slot(); 216*aba80048SShengzhou Liu return 0; 217*aba80048SShengzhou Liu } 218*aba80048SShengzhou Liu 219*aba80048SShengzhou Liu unsigned long get_board_sys_clk(void) 220*aba80048SShengzhou Liu { 221*aba80048SShengzhou Liu u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 222*aba80048SShengzhou Liu 223*aba80048SShengzhou Liu switch (sysclk_conf & 0x0F) { 224*aba80048SShengzhou Liu case QIXIS_SYSCLK_64: 225*aba80048SShengzhou Liu return 64000000; 226*aba80048SShengzhou Liu case QIXIS_SYSCLK_83: 227*aba80048SShengzhou Liu return 83333333; 228*aba80048SShengzhou Liu case QIXIS_SYSCLK_100: 229*aba80048SShengzhou Liu return 100000000; 230*aba80048SShengzhou Liu case QIXIS_SYSCLK_125: 231*aba80048SShengzhou Liu return 125000000; 232*aba80048SShengzhou Liu case QIXIS_SYSCLK_133: 233*aba80048SShengzhou Liu return 133333333; 234*aba80048SShengzhou Liu case QIXIS_SYSCLK_150: 235*aba80048SShengzhou Liu return 150000000; 236*aba80048SShengzhou Liu case QIXIS_SYSCLK_160: 237*aba80048SShengzhou Liu return 160000000; 238*aba80048SShengzhou Liu case QIXIS_SYSCLK_166: 239*aba80048SShengzhou Liu return 166666666; 240*aba80048SShengzhou Liu } 241*aba80048SShengzhou Liu return 66666666; 242*aba80048SShengzhou Liu } 243*aba80048SShengzhou Liu 244*aba80048SShengzhou Liu unsigned long get_board_ddr_clk(void) 245*aba80048SShengzhou Liu { 246*aba80048SShengzhou Liu u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 247*aba80048SShengzhou Liu 248*aba80048SShengzhou Liu switch ((ddrclk_conf & 0x30) >> 4) { 249*aba80048SShengzhou Liu case QIXIS_DDRCLK_100: 250*aba80048SShengzhou Liu return 100000000; 251*aba80048SShengzhou Liu case QIXIS_DDRCLK_125: 252*aba80048SShengzhou Liu return 125000000; 253*aba80048SShengzhou Liu case QIXIS_DDRCLK_133: 254*aba80048SShengzhou Liu return 133333333; 255*aba80048SShengzhou Liu } 256*aba80048SShengzhou Liu return 66666666; 257*aba80048SShengzhou Liu } 258*aba80048SShengzhou Liu 259*aba80048SShengzhou Liu #define NUM_SRDS_PLL 2 260*aba80048SShengzhou Liu int misc_init_r(void) 261*aba80048SShengzhou Liu { 262*aba80048SShengzhou Liu #ifdef CONFIG_PPC_T1024 263*aba80048SShengzhou Liu board_mux_setup(); 264*aba80048SShengzhou Liu #endif 265*aba80048SShengzhou Liu return 0; 266*aba80048SShengzhou Liu } 267*aba80048SShengzhou Liu 268*aba80048SShengzhou Liu int ft_board_setup(void *blob, bd_t *bd) 269*aba80048SShengzhou Liu { 270*aba80048SShengzhou Liu phys_addr_t base; 271*aba80048SShengzhou Liu phys_size_t size; 272*aba80048SShengzhou Liu 273*aba80048SShengzhou Liu ft_cpu_setup(blob, bd); 274*aba80048SShengzhou Liu 275*aba80048SShengzhou Liu base = getenv_bootm_low(); 276*aba80048SShengzhou Liu size = getenv_bootm_size(); 277*aba80048SShengzhou Liu 278*aba80048SShengzhou Liu fdt_fixup_memory(blob, (u64)base, (u64)size); 279*aba80048SShengzhou Liu 280*aba80048SShengzhou Liu #ifdef CONFIG_PCI 281*aba80048SShengzhou Liu pci_of_setup(blob, bd); 282*aba80048SShengzhou Liu #endif 283*aba80048SShengzhou Liu 284*aba80048SShengzhou Liu fdt_fixup_liodn(blob); 285*aba80048SShengzhou Liu 286*aba80048SShengzhou Liu #ifdef CONFIG_HAS_FSL_DR_USB 287*aba80048SShengzhou Liu fdt_fixup_dr_usb(blob, bd); 288*aba80048SShengzhou Liu #endif 289*aba80048SShengzhou Liu 290*aba80048SShengzhou Liu #ifdef CONFIG_SYS_DPAA_FMAN 291*aba80048SShengzhou Liu fdt_fixup_fman_ethernet(blob); 292*aba80048SShengzhou Liu fdt_fixup_board_enet(blob); 293*aba80048SShengzhou Liu #endif 294*aba80048SShengzhou Liu 295*aba80048SShengzhou Liu return 0; 296*aba80048SShengzhou Liu } 297*aba80048SShengzhou Liu 298*aba80048SShengzhou Liu void qixis_dump_switch(void) 299*aba80048SShengzhou Liu { 300*aba80048SShengzhou Liu int i, nr_of_cfgsw; 301*aba80048SShengzhou Liu 302*aba80048SShengzhou Liu QIXIS_WRITE(cms[0], 0x00); 303*aba80048SShengzhou Liu nr_of_cfgsw = QIXIS_READ(cms[1]); 304*aba80048SShengzhou Liu 305*aba80048SShengzhou Liu puts("DIP switch settings dump:\n"); 306*aba80048SShengzhou Liu for (i = 1; i <= nr_of_cfgsw; i++) { 307*aba80048SShengzhou Liu QIXIS_WRITE(cms[0], i); 308*aba80048SShengzhou Liu printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); 309*aba80048SShengzhou Liu } 310*aba80048SShengzhou Liu } 311*aba80048SShengzhou Liu 312*aba80048SShengzhou Liu #ifdef CONFIG_DEEP_SLEEP 313*aba80048SShengzhou Liu void board_mem_sleep_setup(void) 314*aba80048SShengzhou Liu { 315*aba80048SShengzhou Liu /* does not provide HW signals for power management */ 316*aba80048SShengzhou Liu QIXIS_WRITE(pwr_ctl[1], (QIXIS_READ(pwr_ctl[1]) & ~0x2)); 317*aba80048SShengzhou Liu /* Disable MCKE isolation */ 318*aba80048SShengzhou Liu gpio_set_value(2, 0); 319*aba80048SShengzhou Liu udelay(1); 320*aba80048SShengzhou Liu } 321*aba80048SShengzhou Liu #endif 322