1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2aba80048SShengzhou Liu /* 3aba80048SShengzhou Liu * Copyright 2014 Freescale Semiconductor, Inc. 4aba80048SShengzhou Liu */ 5aba80048SShengzhou Liu 6aba80048SShengzhou Liu #include <common.h> 7aba80048SShengzhou Liu #include <command.h> 8aba80048SShengzhou Liu #include <i2c.h> 9aba80048SShengzhou Liu #include <netdev.h> 10aba80048SShengzhou Liu #include <linux/compiler.h> 11aba80048SShengzhou Liu #include <asm/mmu.h> 12aba80048SShengzhou Liu #include <asm/processor.h> 13aba80048SShengzhou Liu #include <asm/cache.h> 14aba80048SShengzhou Liu #include <asm/immap_85xx.h> 15aba80048SShengzhou Liu #include <asm/fsl_law.h> 16aba80048SShengzhou Liu #include <asm/fsl_serdes.h> 17aba80048SShengzhou Liu #include <asm/fsl_liodn.h> 18aba80048SShengzhou Liu #include <fm_eth.h> 19aba80048SShengzhou Liu #include <hwconfig.h> 20aba80048SShengzhou Liu #include "../common/qixis.h" 21aba80048SShengzhou Liu #include "t102xqds.h" 22aba80048SShengzhou Liu #include "t102xqds_qixis.h" 232c537642Stang yuantian #include "../common/sleep.h" 24aba80048SShengzhou Liu 25aba80048SShengzhou Liu DECLARE_GLOBAL_DATA_PTR; 26aba80048SShengzhou Liu 27aba80048SShengzhou Liu int checkboard(void) 28aba80048SShengzhou Liu { 29aba80048SShengzhou Liu char buf[64]; 30aba80048SShengzhou Liu struct cpu_type *cpu = gd->arch.cpu; 31aba80048SShengzhou Liu static const char *const freq[] = {"100", "125", "156.25", "100.0"}; 32aba80048SShengzhou Liu int clock; 33aba80048SShengzhou Liu u8 sw = QIXIS_READ(arch); 34aba80048SShengzhou Liu 35aba80048SShengzhou Liu printf("Board: %sQDS, ", cpu->name); 36aba80048SShengzhou Liu printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4); 37aba80048SShengzhou Liu printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1); 38aba80048SShengzhou Liu 39aba80048SShengzhou Liu #ifdef CONFIG_SDCARD 40aba80048SShengzhou Liu puts("SD/MMC\n"); 41aba80048SShengzhou Liu #elif CONFIG_SPIFLASH 42aba80048SShengzhou Liu puts("SPI\n"); 43aba80048SShengzhou Liu #else 44aba80048SShengzhou Liu sw = QIXIS_READ(brdcfg[0]); 45aba80048SShengzhou Liu sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 46aba80048SShengzhou Liu 47aba80048SShengzhou Liu if (sw < 0x8) 48aba80048SShengzhou Liu printf("vBank: %d\n", sw); 49aba80048SShengzhou Liu else if (sw == 0x8) 50aba80048SShengzhou Liu puts("PromJet\n"); 51aba80048SShengzhou Liu else if (sw == 0x9) 52aba80048SShengzhou Liu puts("NAND\n"); 53aba80048SShengzhou Liu else if (sw == 0x15) 54aba80048SShengzhou Liu printf("IFC Card\n"); 55aba80048SShengzhou Liu else 56aba80048SShengzhou Liu printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 57aba80048SShengzhou Liu #endif 58aba80048SShengzhou Liu 59aba80048SShengzhou Liu printf("FPGA: v%d (%s), build %d", 60aba80048SShengzhou Liu (int)QIXIS_READ(scver), qixis_read_tag(buf), 61aba80048SShengzhou Liu (int)qixis_read_minor()); 62aba80048SShengzhou Liu /* the timestamp string contains "\n" at the end */ 63aba80048SShengzhou Liu printf(" on %s", qixis_read_time(buf)); 64aba80048SShengzhou Liu 65aba80048SShengzhou Liu puts("SERDES Reference: "); 66aba80048SShengzhou Liu sw = QIXIS_READ(brdcfg[2]); 67aba80048SShengzhou Liu clock = (sw >> 6) & 3; 68aba80048SShengzhou Liu printf("Clock1=%sMHz ", freq[clock]); 69aba80048SShengzhou Liu clock = (sw >> 4) & 3; 70aba80048SShengzhou Liu printf("Clock2=%sMHz\n", freq[clock]); 71aba80048SShengzhou Liu 72aba80048SShengzhou Liu return 0; 73aba80048SShengzhou Liu } 74aba80048SShengzhou Liu 75aba80048SShengzhou Liu int select_i2c_ch_pca9547(u8 ch) 76aba80048SShengzhou Liu { 77aba80048SShengzhou Liu int ret; 78aba80048SShengzhou Liu 79aba80048SShengzhou Liu ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); 80aba80048SShengzhou Liu if (ret) { 81aba80048SShengzhou Liu puts("PCA: failed to select proper channel\n"); 82aba80048SShengzhou Liu return ret; 83aba80048SShengzhou Liu } 84aba80048SShengzhou Liu 85aba80048SShengzhou Liu return 0; 86aba80048SShengzhou Liu } 87aba80048SShengzhou Liu 88aba80048SShengzhou Liu static int board_mux_lane_to_slot(void) 89aba80048SShengzhou Liu { 90aba80048SShengzhou Liu ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 91aba80048SShengzhou Liu u32 srds_prtcl_s1; 92aba80048SShengzhou Liu u8 brdcfg9; 93aba80048SShengzhou Liu 94aba80048SShengzhou Liu srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & 95aba80048SShengzhou Liu FSL_CORENET2_RCWSR4_SRDS1_PRTCL; 96aba80048SShengzhou Liu srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; 97aba80048SShengzhou Liu 98aba80048SShengzhou Liu 99aba80048SShengzhou Liu brdcfg9 = QIXIS_READ(brdcfg[9]); 100aba80048SShengzhou Liu QIXIS_WRITE(brdcfg[9], brdcfg9 | BRDCFG9_XFI_TX_DISABLE); 101aba80048SShengzhou Liu 102aba80048SShengzhou Liu switch (srds_prtcl_s1) { 103aba80048SShengzhou Liu case 0: 104aba80048SShengzhou Liu /* SerDes1 is not enabled */ 105aba80048SShengzhou Liu break; 106aba80048SShengzhou Liu case 0xd5: 107aba80048SShengzhou Liu case 0x5b: 108aba80048SShengzhou Liu case 0x6b: 109aba80048SShengzhou Liu case 0x77: 110aba80048SShengzhou Liu case 0x6f: 111aba80048SShengzhou Liu case 0x7f: 112aba80048SShengzhou Liu QIXIS_WRITE(brdcfg[12], 0x8c); 113aba80048SShengzhou Liu break; 114aba80048SShengzhou Liu case 0x40: 115aba80048SShengzhou Liu QIXIS_WRITE(brdcfg[12], 0xfc); 116aba80048SShengzhou Liu break; 117aba80048SShengzhou Liu case 0xd6: 118aba80048SShengzhou Liu case 0x5a: 119aba80048SShengzhou Liu case 0x6a: 120aba80048SShengzhou Liu case 0x56: 121aba80048SShengzhou Liu QIXIS_WRITE(brdcfg[12], 0x88); 122aba80048SShengzhou Liu break; 123aba80048SShengzhou Liu case 0x47: 124aba80048SShengzhou Liu QIXIS_WRITE(brdcfg[12], 0xcc); 125aba80048SShengzhou Liu break; 126aba80048SShengzhou Liu case 0x46: 127aba80048SShengzhou Liu QIXIS_WRITE(brdcfg[12], 0xc8); 128aba80048SShengzhou Liu break; 129aba80048SShengzhou Liu case 0x95: 130aba80048SShengzhou Liu case 0x99: 131aba80048SShengzhou Liu brdcfg9 &= ~BRDCFG9_XFI_TX_DISABLE; 132aba80048SShengzhou Liu QIXIS_WRITE(brdcfg[9], brdcfg9); 133aba80048SShengzhou Liu QIXIS_WRITE(brdcfg[12], 0x8c); 134aba80048SShengzhou Liu break; 135aba80048SShengzhou Liu case 0x116: 136aba80048SShengzhou Liu QIXIS_WRITE(brdcfg[12], 0x00); 137aba80048SShengzhou Liu break; 138aba80048SShengzhou Liu case 0x115: 139aba80048SShengzhou Liu case 0x119: 140aba80048SShengzhou Liu case 0x129: 141aba80048SShengzhou Liu case 0x12b: 142aba80048SShengzhou Liu /* Aurora, PCIe, SGMII, SATA */ 143aba80048SShengzhou Liu QIXIS_WRITE(brdcfg[12], 0x04); 144aba80048SShengzhou Liu break; 145aba80048SShengzhou Liu default: 146aba80048SShengzhou Liu printf("WARNING: unsupported for SerDes Protocol %d\n", 147aba80048SShengzhou Liu srds_prtcl_s1); 148aba80048SShengzhou Liu return -1; 149aba80048SShengzhou Liu } 150aba80048SShengzhou Liu 151aba80048SShengzhou Liu return 0; 152aba80048SShengzhou Liu } 153aba80048SShengzhou Liu 154e5d5f5a8SYork Sun #ifdef CONFIG_ARCH_T1024 155aba80048SShengzhou Liu static void board_mux_setup(void) 156aba80048SShengzhou Liu { 157aba80048SShengzhou Liu u8 brdcfg15; 158aba80048SShengzhou Liu 159aba80048SShengzhou Liu brdcfg15 = QIXIS_READ(brdcfg[15]); 160aba80048SShengzhou Liu brdcfg15 &= ~BRDCFG15_DIUSEL_MASK; 161aba80048SShengzhou Liu 162aba80048SShengzhou Liu if (hwconfig_arg_cmp("pin_mux", "tdm")) { 163aba80048SShengzhou Liu /* Route QE_TDM multiplexed signals to TDM Riser slot */ 164aba80048SShengzhou Liu QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_TDM); 165aba80048SShengzhou Liu QIXIS_WRITE(brdcfg[13], BRDCFG13_TDM_INTERFACE << 2); 166355b3858SShengzhou Liu QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) & 167355b3858SShengzhou Liu ~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_TDM); 168aba80048SShengzhou Liu } else if (hwconfig_arg_cmp("pin_mux", "ucc")) { 169aba80048SShengzhou Liu /* to UCC (ProfiBus) interface */ 170aba80048SShengzhou Liu QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_UCC); 171aba80048SShengzhou Liu } else if (hwconfig_arg_cmp("pin_mux", "hdmi")) { 172aba80048SShengzhou Liu /* to DVI (HDMI) encoder */ 173aba80048SShengzhou Liu QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_HDMI); 174aba80048SShengzhou Liu } else if (hwconfig_arg_cmp("pin_mux", "lcd")) { 175aba80048SShengzhou Liu /* to DFP (LCD) encoder */ 176aba80048SShengzhou Liu QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_LCDFM | 177aba80048SShengzhou Liu BRDCFG15_LCDPD | BRDCFG15_DIUSEL_LCD); 178aba80048SShengzhou Liu } 179355b3858SShengzhou Liu 180355b3858SShengzhou Liu if (hwconfig_arg_cmp("adaptor", "sdxc")) 181355b3858SShengzhou Liu /* Route SPI_CS multiplexed signals to SD slot */ 182355b3858SShengzhou Liu QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) & 183355b3858SShengzhou Liu ~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_SDHC); 184aba80048SShengzhou Liu } 185aba80048SShengzhou Liu #endif 186aba80048SShengzhou Liu 18710227aaaSShengzhou Liu void board_retimer_ds125df111_init(void) 18810227aaaSShengzhou Liu { 18910227aaaSShengzhou Liu u8 reg; 19010227aaaSShengzhou Liu 19110227aaaSShengzhou Liu /* Retimer DS125DF111 is connected to I2C1_CH7_CH5 */ 19210227aaaSShengzhou Liu reg = I2C_MUX_CH7; 19310227aaaSShengzhou Liu i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, ®, 1); 19410227aaaSShengzhou Liu reg = I2C_MUX_CH5; 19510227aaaSShengzhou Liu i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, ®, 1); 19610227aaaSShengzhou Liu 19710227aaaSShengzhou Liu /* Access to Control/Shared register */ 19810227aaaSShengzhou Liu reg = 0x0; 19910227aaaSShengzhou Liu i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); 20010227aaaSShengzhou Liu 20110227aaaSShengzhou Liu /* Read device revision and ID */ 20210227aaaSShengzhou Liu i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1); 20310227aaaSShengzhou Liu debug("Retimer version id = 0x%x\n", reg); 20410227aaaSShengzhou Liu 20510227aaaSShengzhou Liu /* Enable Broadcast */ 20610227aaaSShengzhou Liu reg = 0x0c; 20710227aaaSShengzhou Liu i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); 20810227aaaSShengzhou Liu 20910227aaaSShengzhou Liu /* Reset Channel Registers */ 21010227aaaSShengzhou Liu i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1); 21110227aaaSShengzhou Liu reg |= 0x4; 21210227aaaSShengzhou Liu i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1); 21310227aaaSShengzhou Liu 21410227aaaSShengzhou Liu /* Enable override divider select and Enable Override Output Mux */ 21510227aaaSShengzhou Liu i2c_read(I2C_RETIMER_ADDR, 9, 1, ®, 1); 21610227aaaSShengzhou Liu reg |= 0x24; 21710227aaaSShengzhou Liu i2c_write(I2C_RETIMER_ADDR, 9, 1, ®, 1); 21810227aaaSShengzhou Liu 21910227aaaSShengzhou Liu /* Select VCO Divider to full rate (000) */ 22010227aaaSShengzhou Liu i2c_read(I2C_RETIMER_ADDR, 0x18, 1, ®, 1); 22110227aaaSShengzhou Liu reg &= 0x8f; 22210227aaaSShengzhou Liu i2c_write(I2C_RETIMER_ADDR, 0x18, 1, ®, 1); 22310227aaaSShengzhou Liu 22410227aaaSShengzhou Liu /* Select active PFD MUX input as re-timed data (001) */ 22510227aaaSShengzhou Liu i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1); 22610227aaaSShengzhou Liu reg &= 0x3f; 22710227aaaSShengzhou Liu reg |= 0x20; 22810227aaaSShengzhou Liu i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1); 22910227aaaSShengzhou Liu 23010227aaaSShengzhou Liu /* Set data rate as 10.3125 Gbps */ 23110227aaaSShengzhou Liu reg = 0x0; 23210227aaaSShengzhou Liu i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1); 23310227aaaSShengzhou Liu reg = 0xb2; 23410227aaaSShengzhou Liu i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1); 23510227aaaSShengzhou Liu reg = 0x90; 23610227aaaSShengzhou Liu i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1); 23710227aaaSShengzhou Liu reg = 0xb3; 23810227aaaSShengzhou Liu i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1); 23910227aaaSShengzhou Liu reg = 0xcd; 24010227aaaSShengzhou Liu i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1); 24110227aaaSShengzhou Liu } 24210227aaaSShengzhou Liu 2432c537642Stang yuantian int board_early_init_f(void) 2442c537642Stang yuantian { 2452c537642Stang yuantian #if defined(CONFIG_DEEP_SLEEP) 2462c537642Stang yuantian if (is_warm_boot()) 2472c537642Stang yuantian fsl_dp_disable_console(); 2482c537642Stang yuantian #endif 2492c537642Stang yuantian 2502c537642Stang yuantian return 0; 2512c537642Stang yuantian } 2522c537642Stang yuantian 253aba80048SShengzhou Liu int board_early_init_r(void) 254aba80048SShengzhou Liu { 255aba80048SShengzhou Liu #ifdef CONFIG_SYS_FLASH_BASE 256aba80048SShengzhou Liu const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 257aba80048SShengzhou Liu int flash_esel = find_tlb_idx((void *)flashbase, 1); 258aba80048SShengzhou Liu 259aba80048SShengzhou Liu /* 260aba80048SShengzhou Liu * Remap Boot flash + PROMJET region to caching-inhibited 261aba80048SShengzhou Liu * so that flash can be erased properly. 262aba80048SShengzhou Liu */ 263aba80048SShengzhou Liu 264aba80048SShengzhou Liu /* Flush d-cache and invalidate i-cache of any FLASH data */ 265aba80048SShengzhou Liu flush_dcache(); 266aba80048SShengzhou Liu invalidate_icache(); 267aba80048SShengzhou Liu 268aba80048SShengzhou Liu if (flash_esel == -1) { 269aba80048SShengzhou Liu /* very unlikely unless something is messed up */ 270aba80048SShengzhou Liu puts("Error: Could not find TLB for FLASH BASE\n"); 271aba80048SShengzhou Liu flash_esel = 2; /* give our best effort to continue */ 272aba80048SShengzhou Liu } else { 273aba80048SShengzhou Liu /* invalidate existing TLB entry for flash + promjet */ 274aba80048SShengzhou Liu disable_tlb(flash_esel); 275aba80048SShengzhou Liu } 276aba80048SShengzhou Liu 277aba80048SShengzhou Liu set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, 278aba80048SShengzhou Liu MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 279aba80048SShengzhou Liu 0, flash_esel, BOOKE_PAGESZ_256M, 1); 280aba80048SShengzhou Liu #endif 281aba80048SShengzhou Liu select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 282aba80048SShengzhou Liu board_mux_lane_to_slot(); 28310227aaaSShengzhou Liu board_retimer_ds125df111_init(); 2845818643bSShengzhou Liu 2855818643bSShengzhou Liu /* Increase IO drive strength to address FCS error on RGMII */ 2865818643bSShengzhou Liu out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR, 0xbfdb7800); 2875818643bSShengzhou Liu 288aba80048SShengzhou Liu return 0; 289aba80048SShengzhou Liu } 290aba80048SShengzhou Liu 291aba80048SShengzhou Liu unsigned long get_board_sys_clk(void) 292aba80048SShengzhou Liu { 293aba80048SShengzhou Liu u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 294aba80048SShengzhou Liu 295aba80048SShengzhou Liu switch (sysclk_conf & 0x0F) { 296aba80048SShengzhou Liu case QIXIS_SYSCLK_64: 297aba80048SShengzhou Liu return 64000000; 298aba80048SShengzhou Liu case QIXIS_SYSCLK_83: 299aba80048SShengzhou Liu return 83333333; 300aba80048SShengzhou Liu case QIXIS_SYSCLK_100: 301aba80048SShengzhou Liu return 100000000; 302aba80048SShengzhou Liu case QIXIS_SYSCLK_125: 303aba80048SShengzhou Liu return 125000000; 304aba80048SShengzhou Liu case QIXIS_SYSCLK_133: 305aba80048SShengzhou Liu return 133333333; 306aba80048SShengzhou Liu case QIXIS_SYSCLK_150: 307aba80048SShengzhou Liu return 150000000; 308aba80048SShengzhou Liu case QIXIS_SYSCLK_160: 309aba80048SShengzhou Liu return 160000000; 310aba80048SShengzhou Liu case QIXIS_SYSCLK_166: 311aba80048SShengzhou Liu return 166666666; 312aba80048SShengzhou Liu } 313aba80048SShengzhou Liu return 66666666; 314aba80048SShengzhou Liu } 315aba80048SShengzhou Liu 316aba80048SShengzhou Liu unsigned long get_board_ddr_clk(void) 317aba80048SShengzhou Liu { 318aba80048SShengzhou Liu u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 319aba80048SShengzhou Liu 320aba80048SShengzhou Liu switch ((ddrclk_conf & 0x30) >> 4) { 321aba80048SShengzhou Liu case QIXIS_DDRCLK_100: 322aba80048SShengzhou Liu return 100000000; 323aba80048SShengzhou Liu case QIXIS_DDRCLK_125: 324aba80048SShengzhou Liu return 125000000; 325aba80048SShengzhou Liu case QIXIS_DDRCLK_133: 326aba80048SShengzhou Liu return 133333333; 327aba80048SShengzhou Liu } 328aba80048SShengzhou Liu return 66666666; 329aba80048SShengzhou Liu } 330aba80048SShengzhou Liu 331aba80048SShengzhou Liu #define NUM_SRDS_PLL 2 332aba80048SShengzhou Liu int misc_init_r(void) 333aba80048SShengzhou Liu { 334e5d5f5a8SYork Sun #ifdef CONFIG_ARCH_T1024 335aba80048SShengzhou Liu board_mux_setup(); 336aba80048SShengzhou Liu #endif 337aba80048SShengzhou Liu return 0; 338aba80048SShengzhou Liu } 339aba80048SShengzhou Liu 340355b3858SShengzhou Liu void fdt_fixup_spi_mux(void *blob) 341355b3858SShengzhou Liu { 342355b3858SShengzhou Liu int nodeoff = 0; 343355b3858SShengzhou Liu 344355b3858SShengzhou Liu if (hwconfig_arg_cmp("pin_mux", "tdm")) { 345355b3858SShengzhou Liu while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, 346355b3858SShengzhou Liu "eon,en25s64")) >= 0) { 347355b3858SShengzhou Liu fdt_del_node(blob, nodeoff); 348355b3858SShengzhou Liu } 349355b3858SShengzhou Liu } else { 350355b3858SShengzhou Liu /* remove tdm node */ 351355b3858SShengzhou Liu while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, 352355b3858SShengzhou Liu "maxim,ds26522")) >= 0) { 353355b3858SShengzhou Liu fdt_del_node(blob, nodeoff); 354355b3858SShengzhou Liu } 355355b3858SShengzhou Liu } 356355b3858SShengzhou Liu } 357355b3858SShengzhou Liu 358aba80048SShengzhou Liu int ft_board_setup(void *blob, bd_t *bd) 359aba80048SShengzhou Liu { 360aba80048SShengzhou Liu phys_addr_t base; 361aba80048SShengzhou Liu phys_size_t size; 362aba80048SShengzhou Liu 363aba80048SShengzhou Liu ft_cpu_setup(blob, bd); 364aba80048SShengzhou Liu 365723806ccSSimon Glass base = env_get_bootm_low(); 366723806ccSSimon Glass size = env_get_bootm_size(); 367aba80048SShengzhou Liu 368aba80048SShengzhou Liu fdt_fixup_memory(blob, (u64)base, (u64)size); 369aba80048SShengzhou Liu 370aba80048SShengzhou Liu #ifdef CONFIG_PCI 371aba80048SShengzhou Liu pci_of_setup(blob, bd); 372aba80048SShengzhou Liu #endif 373aba80048SShengzhou Liu 374aba80048SShengzhou Liu fdt_fixup_liodn(blob); 375aba80048SShengzhou Liu 376aba80048SShengzhou Liu #ifdef CONFIG_HAS_FSL_DR_USB 377a5c289b9SSriram Dash fsl_fdt_fixup_dr_usb(blob, bd); 378aba80048SShengzhou Liu #endif 379aba80048SShengzhou Liu 380aba80048SShengzhou Liu #ifdef CONFIG_SYS_DPAA_FMAN 381aba80048SShengzhou Liu fdt_fixup_fman_ethernet(blob); 382aba80048SShengzhou Liu fdt_fixup_board_enet(blob); 383aba80048SShengzhou Liu #endif 384355b3858SShengzhou Liu fdt_fixup_spi_mux(blob); 385aba80048SShengzhou Liu 386aba80048SShengzhou Liu return 0; 387aba80048SShengzhou Liu } 388aba80048SShengzhou Liu 389aba80048SShengzhou Liu void qixis_dump_switch(void) 390aba80048SShengzhou Liu { 391aba80048SShengzhou Liu int i, nr_of_cfgsw; 392aba80048SShengzhou Liu 393aba80048SShengzhou Liu QIXIS_WRITE(cms[0], 0x00); 394aba80048SShengzhou Liu nr_of_cfgsw = QIXIS_READ(cms[1]); 395aba80048SShengzhou Liu 396aba80048SShengzhou Liu puts("DIP switch settings dump:\n"); 397aba80048SShengzhou Liu for (i = 1; i <= nr_of_cfgsw; i++) { 398aba80048SShengzhou Liu QIXIS_WRITE(cms[0], i); 399aba80048SShengzhou Liu printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); 400aba80048SShengzhou Liu } 401aba80048SShengzhou Liu } 402