1aba80048SShengzhou Liu /* 2aba80048SShengzhou Liu * Copyright 2014 Freescale Semiconductor, Inc. 3aba80048SShengzhou Liu * 4aba80048SShengzhou Liu * SPDX-License-Identifier: GPL-2.0+ 5aba80048SShengzhou Liu */ 6aba80048SShengzhou Liu 7aba80048SShengzhou Liu #include <common.h> 8aba80048SShengzhou Liu #include <command.h> 9aba80048SShengzhou Liu #include <i2c.h> 10aba80048SShengzhou Liu #include <netdev.h> 11aba80048SShengzhou Liu #include <linux/compiler.h> 12aba80048SShengzhou Liu #include <asm/mmu.h> 13aba80048SShengzhou Liu #include <asm/processor.h> 14aba80048SShengzhou Liu #include <asm/cache.h> 15aba80048SShengzhou Liu #include <asm/immap_85xx.h> 16aba80048SShengzhou Liu #include <asm/fsl_law.h> 17aba80048SShengzhou Liu #include <asm/fsl_serdes.h> 18aba80048SShengzhou Liu #include <asm/fsl_portals.h> 19aba80048SShengzhou Liu #include <asm/fsl_liodn.h> 20aba80048SShengzhou Liu #include <fm_eth.h> 21aba80048SShengzhou Liu #include <hwconfig.h> 22aba80048SShengzhou Liu #include <asm/mpc85xx_gpio.h> 23aba80048SShengzhou Liu #include "../common/qixis.h" 24aba80048SShengzhou Liu #include "t102xqds.h" 25aba80048SShengzhou Liu #include "t102xqds_qixis.h" 26aba80048SShengzhou Liu 27aba80048SShengzhou Liu DECLARE_GLOBAL_DATA_PTR; 28aba80048SShengzhou Liu 29aba80048SShengzhou Liu int checkboard(void) 30aba80048SShengzhou Liu { 31aba80048SShengzhou Liu char buf[64]; 32aba80048SShengzhou Liu struct cpu_type *cpu = gd->arch.cpu; 33aba80048SShengzhou Liu static const char *const freq[] = {"100", "125", "156.25", "100.0"}; 34aba80048SShengzhou Liu int clock; 35aba80048SShengzhou Liu u8 sw = QIXIS_READ(arch); 36aba80048SShengzhou Liu 37aba80048SShengzhou Liu printf("Board: %sQDS, ", cpu->name); 38aba80048SShengzhou Liu printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4); 39aba80048SShengzhou Liu printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1); 40aba80048SShengzhou Liu 41aba80048SShengzhou Liu #ifdef CONFIG_SDCARD 42aba80048SShengzhou Liu puts("SD/MMC\n"); 43aba80048SShengzhou Liu #elif CONFIG_SPIFLASH 44aba80048SShengzhou Liu puts("SPI\n"); 45aba80048SShengzhou Liu #else 46aba80048SShengzhou Liu sw = QIXIS_READ(brdcfg[0]); 47aba80048SShengzhou Liu sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 48aba80048SShengzhou Liu 49aba80048SShengzhou Liu if (sw < 0x8) 50aba80048SShengzhou Liu printf("vBank: %d\n", sw); 51aba80048SShengzhou Liu else if (sw == 0x8) 52aba80048SShengzhou Liu puts("PromJet\n"); 53aba80048SShengzhou Liu else if (sw == 0x9) 54aba80048SShengzhou Liu puts("NAND\n"); 55aba80048SShengzhou Liu else if (sw == 0x15) 56aba80048SShengzhou Liu printf("IFC Card\n"); 57aba80048SShengzhou Liu else 58aba80048SShengzhou Liu printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 59aba80048SShengzhou Liu #endif 60aba80048SShengzhou Liu 61aba80048SShengzhou Liu printf("FPGA: v%d (%s), build %d", 62aba80048SShengzhou Liu (int)QIXIS_READ(scver), qixis_read_tag(buf), 63aba80048SShengzhou Liu (int)qixis_read_minor()); 64aba80048SShengzhou Liu /* the timestamp string contains "\n" at the end */ 65aba80048SShengzhou Liu printf(" on %s", qixis_read_time(buf)); 66aba80048SShengzhou Liu 67aba80048SShengzhou Liu puts("SERDES Reference: "); 68aba80048SShengzhou Liu sw = QIXIS_READ(brdcfg[2]); 69aba80048SShengzhou Liu clock = (sw >> 6) & 3; 70aba80048SShengzhou Liu printf("Clock1=%sMHz ", freq[clock]); 71aba80048SShengzhou Liu clock = (sw >> 4) & 3; 72aba80048SShengzhou Liu printf("Clock2=%sMHz\n", freq[clock]); 73aba80048SShengzhou Liu 74aba80048SShengzhou Liu return 0; 75aba80048SShengzhou Liu } 76aba80048SShengzhou Liu 77aba80048SShengzhou Liu int select_i2c_ch_pca9547(u8 ch) 78aba80048SShengzhou Liu { 79aba80048SShengzhou Liu int ret; 80aba80048SShengzhou Liu 81aba80048SShengzhou Liu ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); 82aba80048SShengzhou Liu if (ret) { 83aba80048SShengzhou Liu puts("PCA: failed to select proper channel\n"); 84aba80048SShengzhou Liu return ret; 85aba80048SShengzhou Liu } 86aba80048SShengzhou Liu 87aba80048SShengzhou Liu return 0; 88aba80048SShengzhou Liu } 89aba80048SShengzhou Liu 90aba80048SShengzhou Liu static int board_mux_lane_to_slot(void) 91aba80048SShengzhou Liu { 92aba80048SShengzhou Liu ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 93aba80048SShengzhou Liu u32 srds_prtcl_s1; 94aba80048SShengzhou Liu u8 brdcfg9; 95aba80048SShengzhou Liu 96aba80048SShengzhou Liu srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & 97aba80048SShengzhou Liu FSL_CORENET2_RCWSR4_SRDS1_PRTCL; 98aba80048SShengzhou Liu srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; 99aba80048SShengzhou Liu 100aba80048SShengzhou Liu 101aba80048SShengzhou Liu brdcfg9 = QIXIS_READ(brdcfg[9]); 102aba80048SShengzhou Liu QIXIS_WRITE(brdcfg[9], brdcfg9 | BRDCFG9_XFI_TX_DISABLE); 103aba80048SShengzhou Liu 104aba80048SShengzhou Liu switch (srds_prtcl_s1) { 105aba80048SShengzhou Liu case 0: 106aba80048SShengzhou Liu /* SerDes1 is not enabled */ 107aba80048SShengzhou Liu break; 108aba80048SShengzhou Liu case 0xd5: 109aba80048SShengzhou Liu case 0x5b: 110aba80048SShengzhou Liu case 0x6b: 111aba80048SShengzhou Liu case 0x77: 112aba80048SShengzhou Liu case 0x6f: 113aba80048SShengzhou Liu case 0x7f: 114aba80048SShengzhou Liu QIXIS_WRITE(brdcfg[12], 0x8c); 115aba80048SShengzhou Liu break; 116aba80048SShengzhou Liu case 0x40: 117aba80048SShengzhou Liu QIXIS_WRITE(brdcfg[12], 0xfc); 118aba80048SShengzhou Liu break; 119aba80048SShengzhou Liu case 0xd6: 120aba80048SShengzhou Liu case 0x5a: 121aba80048SShengzhou Liu case 0x6a: 122aba80048SShengzhou Liu case 0x56: 123aba80048SShengzhou Liu QIXIS_WRITE(brdcfg[12], 0x88); 124aba80048SShengzhou Liu break; 125aba80048SShengzhou Liu case 0x47: 126aba80048SShengzhou Liu QIXIS_WRITE(brdcfg[12], 0xcc); 127aba80048SShengzhou Liu break; 128aba80048SShengzhou Liu case 0x46: 129aba80048SShengzhou Liu QIXIS_WRITE(brdcfg[12], 0xc8); 130aba80048SShengzhou Liu break; 131aba80048SShengzhou Liu case 0x95: 132aba80048SShengzhou Liu case 0x99: 133aba80048SShengzhou Liu brdcfg9 &= ~BRDCFG9_XFI_TX_DISABLE; 134aba80048SShengzhou Liu QIXIS_WRITE(brdcfg[9], brdcfg9); 135aba80048SShengzhou Liu QIXIS_WRITE(brdcfg[12], 0x8c); 136aba80048SShengzhou Liu break; 137aba80048SShengzhou Liu case 0x116: 138aba80048SShengzhou Liu QIXIS_WRITE(brdcfg[12], 0x00); 139aba80048SShengzhou Liu break; 140aba80048SShengzhou Liu case 0x115: 141aba80048SShengzhou Liu case 0x119: 142aba80048SShengzhou Liu case 0x129: 143aba80048SShengzhou Liu case 0x12b: 144aba80048SShengzhou Liu /* Aurora, PCIe, SGMII, SATA */ 145aba80048SShengzhou Liu QIXIS_WRITE(brdcfg[12], 0x04); 146aba80048SShengzhou Liu break; 147aba80048SShengzhou Liu default: 148aba80048SShengzhou Liu printf("WARNING: unsupported for SerDes Protocol %d\n", 149aba80048SShengzhou Liu srds_prtcl_s1); 150aba80048SShengzhou Liu return -1; 151aba80048SShengzhou Liu } 152aba80048SShengzhou Liu 153aba80048SShengzhou Liu return 0; 154aba80048SShengzhou Liu } 155aba80048SShengzhou Liu 156aba80048SShengzhou Liu #ifdef CONFIG_PPC_T1024 157aba80048SShengzhou Liu static void board_mux_setup(void) 158aba80048SShengzhou Liu { 159aba80048SShengzhou Liu u8 brdcfg15; 160aba80048SShengzhou Liu 161aba80048SShengzhou Liu brdcfg15 = QIXIS_READ(brdcfg[15]); 162aba80048SShengzhou Liu brdcfg15 &= ~BRDCFG15_DIUSEL_MASK; 163aba80048SShengzhou Liu 164aba80048SShengzhou Liu if (hwconfig_arg_cmp("pin_mux", "tdm")) { 165aba80048SShengzhou Liu /* Route QE_TDM multiplexed signals to TDM Riser slot */ 166aba80048SShengzhou Liu QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_TDM); 167aba80048SShengzhou Liu QIXIS_WRITE(brdcfg[13], BRDCFG13_TDM_INTERFACE << 2); 168355b3858SShengzhou Liu QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) & 169355b3858SShengzhou Liu ~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_TDM); 170aba80048SShengzhou Liu } else if (hwconfig_arg_cmp("pin_mux", "ucc")) { 171aba80048SShengzhou Liu /* to UCC (ProfiBus) interface */ 172aba80048SShengzhou Liu QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_UCC); 173aba80048SShengzhou Liu } else if (hwconfig_arg_cmp("pin_mux", "hdmi")) { 174aba80048SShengzhou Liu /* to DVI (HDMI) encoder */ 175aba80048SShengzhou Liu QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_HDMI); 176aba80048SShengzhou Liu } else if (hwconfig_arg_cmp("pin_mux", "lcd")) { 177aba80048SShengzhou Liu /* to DFP (LCD) encoder */ 178aba80048SShengzhou Liu QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_LCDFM | 179aba80048SShengzhou Liu BRDCFG15_LCDPD | BRDCFG15_DIUSEL_LCD); 180aba80048SShengzhou Liu } 181355b3858SShengzhou Liu 182355b3858SShengzhou Liu if (hwconfig_arg_cmp("adaptor", "sdxc")) 183355b3858SShengzhou Liu /* Route SPI_CS multiplexed signals to SD slot */ 184355b3858SShengzhou Liu QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) & 185355b3858SShengzhou Liu ~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_SDHC); 186aba80048SShengzhou Liu } 187aba80048SShengzhou Liu #endif 188aba80048SShengzhou Liu 189*10227aaaSShengzhou Liu void board_retimer_ds125df111_init(void) 190*10227aaaSShengzhou Liu { 191*10227aaaSShengzhou Liu u8 reg; 192*10227aaaSShengzhou Liu 193*10227aaaSShengzhou Liu /* Retimer DS125DF111 is connected to I2C1_CH7_CH5 */ 194*10227aaaSShengzhou Liu reg = I2C_MUX_CH7; 195*10227aaaSShengzhou Liu i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, ®, 1); 196*10227aaaSShengzhou Liu reg = I2C_MUX_CH5; 197*10227aaaSShengzhou Liu i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, ®, 1); 198*10227aaaSShengzhou Liu 199*10227aaaSShengzhou Liu /* Access to Control/Shared register */ 200*10227aaaSShengzhou Liu reg = 0x0; 201*10227aaaSShengzhou Liu i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); 202*10227aaaSShengzhou Liu 203*10227aaaSShengzhou Liu /* Read device revision and ID */ 204*10227aaaSShengzhou Liu i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1); 205*10227aaaSShengzhou Liu debug("Retimer version id = 0x%x\n", reg); 206*10227aaaSShengzhou Liu 207*10227aaaSShengzhou Liu /* Enable Broadcast */ 208*10227aaaSShengzhou Liu reg = 0x0c; 209*10227aaaSShengzhou Liu i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); 210*10227aaaSShengzhou Liu 211*10227aaaSShengzhou Liu /* Reset Channel Registers */ 212*10227aaaSShengzhou Liu i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1); 213*10227aaaSShengzhou Liu reg |= 0x4; 214*10227aaaSShengzhou Liu i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1); 215*10227aaaSShengzhou Liu 216*10227aaaSShengzhou Liu /* Enable override divider select and Enable Override Output Mux */ 217*10227aaaSShengzhou Liu i2c_read(I2C_RETIMER_ADDR, 9, 1, ®, 1); 218*10227aaaSShengzhou Liu reg |= 0x24; 219*10227aaaSShengzhou Liu i2c_write(I2C_RETIMER_ADDR, 9, 1, ®, 1); 220*10227aaaSShengzhou Liu 221*10227aaaSShengzhou Liu /* Select VCO Divider to full rate (000) */ 222*10227aaaSShengzhou Liu i2c_read(I2C_RETIMER_ADDR, 0x18, 1, ®, 1); 223*10227aaaSShengzhou Liu reg &= 0x8f; 224*10227aaaSShengzhou Liu i2c_write(I2C_RETIMER_ADDR, 0x18, 1, ®, 1); 225*10227aaaSShengzhou Liu 226*10227aaaSShengzhou Liu /* Select active PFD MUX input as re-timed data (001) */ 227*10227aaaSShengzhou Liu i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1); 228*10227aaaSShengzhou Liu reg &= 0x3f; 229*10227aaaSShengzhou Liu reg |= 0x20; 230*10227aaaSShengzhou Liu i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1); 231*10227aaaSShengzhou Liu 232*10227aaaSShengzhou Liu /* Set data rate as 10.3125 Gbps */ 233*10227aaaSShengzhou Liu reg = 0x0; 234*10227aaaSShengzhou Liu i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1); 235*10227aaaSShengzhou Liu reg = 0xb2; 236*10227aaaSShengzhou Liu i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1); 237*10227aaaSShengzhou Liu reg = 0x90; 238*10227aaaSShengzhou Liu i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1); 239*10227aaaSShengzhou Liu reg = 0xb3; 240*10227aaaSShengzhou Liu i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1); 241*10227aaaSShengzhou Liu reg = 0xcd; 242*10227aaaSShengzhou Liu i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1); 243*10227aaaSShengzhou Liu } 244*10227aaaSShengzhou Liu 245aba80048SShengzhou Liu int board_early_init_r(void) 246aba80048SShengzhou Liu { 247aba80048SShengzhou Liu #ifdef CONFIG_SYS_FLASH_BASE 248aba80048SShengzhou Liu const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 249aba80048SShengzhou Liu int flash_esel = find_tlb_idx((void *)flashbase, 1); 250aba80048SShengzhou Liu 251aba80048SShengzhou Liu /* 252aba80048SShengzhou Liu * Remap Boot flash + PROMJET region to caching-inhibited 253aba80048SShengzhou Liu * so that flash can be erased properly. 254aba80048SShengzhou Liu */ 255aba80048SShengzhou Liu 256aba80048SShengzhou Liu /* Flush d-cache and invalidate i-cache of any FLASH data */ 257aba80048SShengzhou Liu flush_dcache(); 258aba80048SShengzhou Liu invalidate_icache(); 259aba80048SShengzhou Liu 260aba80048SShengzhou Liu if (flash_esel == -1) { 261aba80048SShengzhou Liu /* very unlikely unless something is messed up */ 262aba80048SShengzhou Liu puts("Error: Could not find TLB for FLASH BASE\n"); 263aba80048SShengzhou Liu flash_esel = 2; /* give our best effort to continue */ 264aba80048SShengzhou Liu } else { 265aba80048SShengzhou Liu /* invalidate existing TLB entry for flash + promjet */ 266aba80048SShengzhou Liu disable_tlb(flash_esel); 267aba80048SShengzhou Liu } 268aba80048SShengzhou Liu 269aba80048SShengzhou Liu set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, 270aba80048SShengzhou Liu MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 271aba80048SShengzhou Liu 0, flash_esel, BOOKE_PAGESZ_256M, 1); 272aba80048SShengzhou Liu #endif 273aba80048SShengzhou Liu set_liodns(); 274aba80048SShengzhou Liu #ifdef CONFIG_SYS_DPAA_QBMAN 275aba80048SShengzhou Liu setup_portals(); 276aba80048SShengzhou Liu #endif 277aba80048SShengzhou Liu select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 278aba80048SShengzhou Liu board_mux_lane_to_slot(); 279*10227aaaSShengzhou Liu board_retimer_ds125df111_init(); 2805818643bSShengzhou Liu 2815818643bSShengzhou Liu /* Increase IO drive strength to address FCS error on RGMII */ 2825818643bSShengzhou Liu out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR, 0xbfdb7800); 2835818643bSShengzhou Liu 284aba80048SShengzhou Liu return 0; 285aba80048SShengzhou Liu } 286aba80048SShengzhou Liu 287aba80048SShengzhou Liu unsigned long get_board_sys_clk(void) 288aba80048SShengzhou Liu { 289aba80048SShengzhou Liu u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 290aba80048SShengzhou Liu 291aba80048SShengzhou Liu switch (sysclk_conf & 0x0F) { 292aba80048SShengzhou Liu case QIXIS_SYSCLK_64: 293aba80048SShengzhou Liu return 64000000; 294aba80048SShengzhou Liu case QIXIS_SYSCLK_83: 295aba80048SShengzhou Liu return 83333333; 296aba80048SShengzhou Liu case QIXIS_SYSCLK_100: 297aba80048SShengzhou Liu return 100000000; 298aba80048SShengzhou Liu case QIXIS_SYSCLK_125: 299aba80048SShengzhou Liu return 125000000; 300aba80048SShengzhou Liu case QIXIS_SYSCLK_133: 301aba80048SShengzhou Liu return 133333333; 302aba80048SShengzhou Liu case QIXIS_SYSCLK_150: 303aba80048SShengzhou Liu return 150000000; 304aba80048SShengzhou Liu case QIXIS_SYSCLK_160: 305aba80048SShengzhou Liu return 160000000; 306aba80048SShengzhou Liu case QIXIS_SYSCLK_166: 307aba80048SShengzhou Liu return 166666666; 308aba80048SShengzhou Liu } 309aba80048SShengzhou Liu return 66666666; 310aba80048SShengzhou Liu } 311aba80048SShengzhou Liu 312aba80048SShengzhou Liu unsigned long get_board_ddr_clk(void) 313aba80048SShengzhou Liu { 314aba80048SShengzhou Liu u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 315aba80048SShengzhou Liu 316aba80048SShengzhou Liu switch ((ddrclk_conf & 0x30) >> 4) { 317aba80048SShengzhou Liu case QIXIS_DDRCLK_100: 318aba80048SShengzhou Liu return 100000000; 319aba80048SShengzhou Liu case QIXIS_DDRCLK_125: 320aba80048SShengzhou Liu return 125000000; 321aba80048SShengzhou Liu case QIXIS_DDRCLK_133: 322aba80048SShengzhou Liu return 133333333; 323aba80048SShengzhou Liu } 324aba80048SShengzhou Liu return 66666666; 325aba80048SShengzhou Liu } 326aba80048SShengzhou Liu 327aba80048SShengzhou Liu #define NUM_SRDS_PLL 2 328aba80048SShengzhou Liu int misc_init_r(void) 329aba80048SShengzhou Liu { 330aba80048SShengzhou Liu #ifdef CONFIG_PPC_T1024 331aba80048SShengzhou Liu board_mux_setup(); 332aba80048SShengzhou Liu #endif 333aba80048SShengzhou Liu return 0; 334aba80048SShengzhou Liu } 335aba80048SShengzhou Liu 336355b3858SShengzhou Liu void fdt_fixup_spi_mux(void *blob) 337355b3858SShengzhou Liu { 338355b3858SShengzhou Liu int nodeoff = 0; 339355b3858SShengzhou Liu 340355b3858SShengzhou Liu if (hwconfig_arg_cmp("pin_mux", "tdm")) { 341355b3858SShengzhou Liu while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, 342355b3858SShengzhou Liu "eon,en25s64")) >= 0) { 343355b3858SShengzhou Liu fdt_del_node(blob, nodeoff); 344355b3858SShengzhou Liu } 345355b3858SShengzhou Liu } else { 346355b3858SShengzhou Liu /* remove tdm node */ 347355b3858SShengzhou Liu while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, 348355b3858SShengzhou Liu "maxim,ds26522")) >= 0) { 349355b3858SShengzhou Liu fdt_del_node(blob, nodeoff); 350355b3858SShengzhou Liu } 351355b3858SShengzhou Liu } 352355b3858SShengzhou Liu } 353355b3858SShengzhou Liu 354aba80048SShengzhou Liu int ft_board_setup(void *blob, bd_t *bd) 355aba80048SShengzhou Liu { 356aba80048SShengzhou Liu phys_addr_t base; 357aba80048SShengzhou Liu phys_size_t size; 358aba80048SShengzhou Liu 359aba80048SShengzhou Liu ft_cpu_setup(blob, bd); 360aba80048SShengzhou Liu 361aba80048SShengzhou Liu base = getenv_bootm_low(); 362aba80048SShengzhou Liu size = getenv_bootm_size(); 363aba80048SShengzhou Liu 364aba80048SShengzhou Liu fdt_fixup_memory(blob, (u64)base, (u64)size); 365aba80048SShengzhou Liu 366aba80048SShengzhou Liu #ifdef CONFIG_PCI 367aba80048SShengzhou Liu pci_of_setup(blob, bd); 368aba80048SShengzhou Liu #endif 369aba80048SShengzhou Liu 370aba80048SShengzhou Liu fdt_fixup_liodn(blob); 371aba80048SShengzhou Liu 372aba80048SShengzhou Liu #ifdef CONFIG_HAS_FSL_DR_USB 373aba80048SShengzhou Liu fdt_fixup_dr_usb(blob, bd); 374aba80048SShengzhou Liu #endif 375aba80048SShengzhou Liu 376aba80048SShengzhou Liu #ifdef CONFIG_SYS_DPAA_FMAN 377aba80048SShengzhou Liu fdt_fixup_fman_ethernet(blob); 378aba80048SShengzhou Liu fdt_fixup_board_enet(blob); 379aba80048SShengzhou Liu #endif 380355b3858SShengzhou Liu fdt_fixup_spi_mux(blob); 381aba80048SShengzhou Liu 382aba80048SShengzhou Liu return 0; 383aba80048SShengzhou Liu } 384aba80048SShengzhou Liu 385aba80048SShengzhou Liu void qixis_dump_switch(void) 386aba80048SShengzhou Liu { 387aba80048SShengzhou Liu int i, nr_of_cfgsw; 388aba80048SShengzhou Liu 389aba80048SShengzhou Liu QIXIS_WRITE(cms[0], 0x00); 390aba80048SShengzhou Liu nr_of_cfgsw = QIXIS_READ(cms[1]); 391aba80048SShengzhou Liu 392aba80048SShengzhou Liu puts("DIP switch settings dump:\n"); 393aba80048SShengzhou Liu for (i = 1; i <= nr_of_cfgsw; i++) { 394aba80048SShengzhou Liu QIXIS_WRITE(cms[0], i); 395aba80048SShengzhou Liu printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); 396aba80048SShengzhou Liu } 397aba80048SShengzhou Liu } 398aba80048SShengzhou Liu 399aba80048SShengzhou Liu #ifdef CONFIG_DEEP_SLEEP 400aba80048SShengzhou Liu void board_mem_sleep_setup(void) 401aba80048SShengzhou Liu { 402aba80048SShengzhou Liu /* does not provide HW signals for power management */ 403aba80048SShengzhou Liu QIXIS_WRITE(pwr_ctl[1], (QIXIS_READ(pwr_ctl[1]) & ~0x2)); 404aba80048SShengzhou Liu /* Disable MCKE isolation */ 405aba80048SShengzhou Liu gpio_set_value(2, 0); 406aba80048SShengzhou Liu udelay(1); 407aba80048SShengzhou Liu } 408aba80048SShengzhou Liu #endif 409