1 /* Copyright 2014 Freescale Semiconductor, Inc. 2 * 3 * SPDX-License-Identifier: GPL-2.0+ 4 */ 5 6 #include <common.h> 7 #include <malloc.h> 8 #include <ns16550.h> 9 #include <nand.h> 10 #include <i2c.h> 11 #include <mmc.h> 12 #include <fsl_esdhc.h> 13 #include <spi_flash.h> 14 #include "../common/qixis.h" 15 #include "t102xqds_qixis.h" 16 17 DECLARE_GLOBAL_DATA_PTR; 18 19 phys_size_t get_effective_memsize(void) 20 { 21 return CONFIG_SYS_L3_SIZE; 22 } 23 24 unsigned long get_board_sys_clk(void) 25 { 26 u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 27 28 switch (sysclk_conf & 0x0F) { 29 case QIXIS_SYSCLK_83: 30 return 83333333; 31 case QIXIS_SYSCLK_100: 32 return 100000000; 33 case QIXIS_SYSCLK_125: 34 return 125000000; 35 case QIXIS_SYSCLK_133: 36 return 133333333; 37 case QIXIS_SYSCLK_150: 38 return 150000000; 39 case QIXIS_SYSCLK_160: 40 return 160000000; 41 case QIXIS_SYSCLK_166: 42 return 166666666; 43 } 44 return 66666666; 45 } 46 47 unsigned long get_board_ddr_clk(void) 48 { 49 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 50 51 switch ((ddrclk_conf & 0x30) >> 4) { 52 case QIXIS_DDRCLK_100: 53 return 100000000; 54 case QIXIS_DDRCLK_125: 55 return 125000000; 56 case QIXIS_DDRCLK_133: 57 return 133333333; 58 } 59 return 66666666; 60 } 61 62 void board_init_f(ulong bootflag) 63 { 64 u32 plat_ratio, sys_clk, ccb_clk; 65 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 66 67 #if defined(CONFIG_PPC_T1040) && defined(CONFIG_SPL_NAND_BOOT) 68 /* 69 * There is T1040 SoC issue where NOR, FPGA are inaccessible during 70 * NAND boot because IFC signals > IFC_AD7 are not enabled. 71 * This workaround changes RCW source to make all signals enabled. 72 */ 73 u32 porsr1, pinctl; 74 #define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000 75 76 porsr1 = in_be32(&gur->porsr1); 77 pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000); 78 out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl); 79 #endif 80 81 /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ 82 memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); 83 84 /* Update GD pointer */ 85 gd = (gd_t *)(CONFIG_SPL_GD_ADDR); 86 87 console_init_f(); 88 89 /* initialize selected port with appropriate baud rate */ 90 sys_clk = get_board_sys_clk(); 91 plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; 92 ccb_clk = sys_clk * plat_ratio / 2; 93 94 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, 95 ccb_clk / 16 / CONFIG_BAUDRATE); 96 97 #if defined(CONFIG_SPL_MMC_BOOT) 98 puts("\nSD boot...\n"); 99 #elif defined(CONFIG_SPL_SPI_BOOT) 100 puts("\nSPI boot...\n"); 101 #elif defined(CONFIG_SPL_NAND_BOOT) 102 puts("\nNAND boot...\n"); 103 #endif 104 105 relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); 106 } 107 108 void board_init_r(gd_t *gd, ulong dest_addr) 109 { 110 bd_t *bd; 111 112 bd = (bd_t *)(gd + sizeof(gd_t)); 113 memset(bd, 0, sizeof(bd_t)); 114 gd->bd = bd; 115 bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; 116 bd->bi_memsize = CONFIG_SYS_L3_SIZE; 117 118 probecpu(); 119 get_clocks(); 120 mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, 121 CONFIG_SPL_RELOC_MALLOC_SIZE); 122 123 #ifdef CONFIG_SPL_NAND_BOOT 124 nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, 125 (uchar *)CONFIG_ENV_ADDR); 126 #endif 127 #ifdef CONFIG_SPL_MMC_BOOT 128 mmc_initialize(bd); 129 mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, 130 (uchar *)CONFIG_ENV_ADDR); 131 #endif 132 #ifdef CONFIG_SPL_SPI_BOOT 133 spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, 134 (uchar *)CONFIG_ENV_ADDR); 135 #endif 136 137 gd->env_addr = (ulong)(CONFIG_ENV_ADDR); 138 gd->env_valid = 1; 139 140 i2c_init_all(); 141 142 gd->ram_size = initdram(0); 143 144 #ifdef CONFIG_SPL_MMC_BOOT 145 mmc_boot(); 146 #elif defined(CONFIG_SPL_SPI_BOOT) 147 spi_boot(); 148 #elif defined(CONFIG_SPL_NAND_BOOT) 149 nand_boot(); 150 #endif 151 } 152