1 /* Copyright 2014 Freescale Semiconductor, Inc. 2 * 3 * SPDX-License-Identifier: GPL-2.0+ 4 */ 5 6 #include <common.h> 7 #include <console.h> 8 #include <malloc.h> 9 #include <ns16550.h> 10 #include <nand.h> 11 #include <i2c.h> 12 #include <mmc.h> 13 #include <fsl_esdhc.h> 14 #include <spi_flash.h> 15 #include "../common/qixis.h" 16 #include "t102xqds_qixis.h" 17 18 DECLARE_GLOBAL_DATA_PTR; 19 20 phys_size_t get_effective_memsize(void) 21 { 22 return CONFIG_SYS_L3_SIZE; 23 } 24 25 unsigned long get_board_sys_clk(void) 26 { 27 u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 28 29 switch (sysclk_conf & 0x0F) { 30 case QIXIS_SYSCLK_83: 31 return 83333333; 32 case QIXIS_SYSCLK_100: 33 return 100000000; 34 case QIXIS_SYSCLK_125: 35 return 125000000; 36 case QIXIS_SYSCLK_133: 37 return 133333333; 38 case QIXIS_SYSCLK_150: 39 return 150000000; 40 case QIXIS_SYSCLK_160: 41 return 160000000; 42 case QIXIS_SYSCLK_166: 43 return 166666666; 44 } 45 return 66666666; 46 } 47 48 unsigned long get_board_ddr_clk(void) 49 { 50 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 51 52 switch ((ddrclk_conf & 0x30) >> 4) { 53 case QIXIS_DDRCLK_100: 54 return 100000000; 55 case QIXIS_DDRCLK_125: 56 return 125000000; 57 case QIXIS_DDRCLK_133: 58 return 133333333; 59 } 60 return 66666666; 61 } 62 63 void board_init_f(ulong bootflag) 64 { 65 u32 plat_ratio, sys_clk, ccb_clk; 66 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 67 68 #if defined(CONFIG_PPC_T1040) && defined(CONFIG_SPL_NAND_BOOT) 69 /* 70 * There is T1040 SoC issue where NOR, FPGA are inaccessible during 71 * NAND boot because IFC signals > IFC_AD7 are not enabled. 72 * This workaround changes RCW source to make all signals enabled. 73 */ 74 u32 porsr1, pinctl; 75 #define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000 76 77 porsr1 = in_be32(&gur->porsr1); 78 pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000); 79 out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl); 80 #endif 81 82 /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ 83 memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); 84 85 /* Update GD pointer */ 86 gd = (gd_t *)(CONFIG_SPL_GD_ADDR); 87 88 console_init_f(); 89 90 /* initialize selected port with appropriate baud rate */ 91 sys_clk = get_board_sys_clk(); 92 plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; 93 ccb_clk = sys_clk * plat_ratio / 2; 94 95 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, 96 ccb_clk / 16 / CONFIG_BAUDRATE); 97 98 #if defined(CONFIG_SPL_MMC_BOOT) 99 puts("\nSD boot...\n"); 100 #elif defined(CONFIG_SPL_SPI_BOOT) 101 puts("\nSPI boot...\n"); 102 #elif defined(CONFIG_SPL_NAND_BOOT) 103 puts("\nNAND boot...\n"); 104 #endif 105 106 relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); 107 } 108 109 void board_init_r(gd_t *gd, ulong dest_addr) 110 { 111 bd_t *bd; 112 113 bd = (bd_t *)(gd + sizeof(gd_t)); 114 memset(bd, 0, sizeof(bd_t)); 115 gd->bd = bd; 116 bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; 117 bd->bi_memsize = CONFIG_SYS_L3_SIZE; 118 119 probecpu(); 120 get_clocks(); 121 mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, 122 CONFIG_SPL_RELOC_MALLOC_SIZE); 123 124 #ifdef CONFIG_SPL_NAND_BOOT 125 nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, 126 (uchar *)CONFIG_ENV_ADDR); 127 #endif 128 #ifdef CONFIG_SPL_MMC_BOOT 129 mmc_initialize(bd); 130 mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, 131 (uchar *)CONFIG_ENV_ADDR); 132 #endif 133 #ifdef CONFIG_SPL_SPI_BOOT 134 spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, 135 (uchar *)CONFIG_ENV_ADDR); 136 #endif 137 138 gd->env_addr = (ulong)(CONFIG_ENV_ADDR); 139 gd->env_valid = 1; 140 141 i2c_init_all(); 142 143 gd->ram_size = initdram(0); 144 145 #ifdef CONFIG_SPL_MMC_BOOT 146 mmc_boot(); 147 #elif defined(CONFIG_SPL_SPI_BOOT) 148 spi_boot(); 149 #elif defined(CONFIG_SPL_NAND_BOOT) 150 nand_boot(); 151 #endif 152 } 153