1 /* Copyright 2014 Freescale Semiconductor, Inc. 2 * 3 * SPDX-License-Identifier: GPL-2.0+ 4 */ 5 6 #include <common.h> 7 #include <console.h> 8 #include <environment.h> 9 #include <malloc.h> 10 #include <ns16550.h> 11 #include <nand.h> 12 #include <i2c.h> 13 #include <mmc.h> 14 #include <fsl_esdhc.h> 15 #include <spi_flash.h> 16 #include "../common/qixis.h" 17 #include "t102xqds_qixis.h" 18 #include "../common/spl.h" 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 phys_size_t get_effective_memsize(void) 23 { 24 return CONFIG_SYS_L3_SIZE; 25 } 26 27 unsigned long get_board_sys_clk(void) 28 { 29 u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 30 31 switch (sysclk_conf & 0x0F) { 32 case QIXIS_SYSCLK_83: 33 return 83333333; 34 case QIXIS_SYSCLK_100: 35 return 100000000; 36 case QIXIS_SYSCLK_125: 37 return 125000000; 38 case QIXIS_SYSCLK_133: 39 return 133333333; 40 case QIXIS_SYSCLK_150: 41 return 150000000; 42 case QIXIS_SYSCLK_160: 43 return 160000000; 44 case QIXIS_SYSCLK_166: 45 return 166666666; 46 } 47 return 66666666; 48 } 49 50 unsigned long get_board_ddr_clk(void) 51 { 52 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 53 54 switch ((ddrclk_conf & 0x30) >> 4) { 55 case QIXIS_DDRCLK_100: 56 return 100000000; 57 case QIXIS_DDRCLK_125: 58 return 125000000; 59 case QIXIS_DDRCLK_133: 60 return 133333333; 61 } 62 return 66666666; 63 } 64 65 void board_init_f(ulong bootflag) 66 { 67 u32 plat_ratio, sys_clk, ccb_clk; 68 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 69 70 #if defined(CONFIG_ARCH_T1040) && defined(CONFIG_SPL_NAND_BOOT) 71 /* 72 * There is T1040 SoC issue where NOR, FPGA are inaccessible during 73 * NAND boot because IFC signals > IFC_AD7 are not enabled. 74 * This workaround changes RCW source to make all signals enabled. 75 */ 76 u32 porsr1, pinctl; 77 #define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000 78 79 porsr1 = in_be32(&gur->porsr1); 80 pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000); 81 out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl); 82 #endif 83 84 /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ 85 memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); 86 87 /* Update GD pointer */ 88 gd = (gd_t *)(CONFIG_SPL_GD_ADDR); 89 90 console_init_f(); 91 92 /* initialize selected port with appropriate baud rate */ 93 sys_clk = get_board_sys_clk(); 94 plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; 95 ccb_clk = sys_clk * plat_ratio / 2; 96 97 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, 98 ccb_clk / 16 / CONFIG_BAUDRATE); 99 100 #if defined(CONFIG_SPL_MMC_BOOT) 101 puts("\nSD boot...\n"); 102 #elif defined(CONFIG_SPL_SPI_BOOT) 103 puts("\nSPI boot...\n"); 104 #elif defined(CONFIG_SPL_NAND_BOOT) 105 puts("\nNAND boot...\n"); 106 #endif 107 108 relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); 109 } 110 111 void board_init_r(gd_t *gd, ulong dest_addr) 112 { 113 bd_t *bd; 114 115 bd = (bd_t *)(gd + sizeof(gd_t)); 116 memset(bd, 0, sizeof(bd_t)); 117 gd->bd = bd; 118 bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; 119 bd->bi_memsize = CONFIG_SYS_L3_SIZE; 120 121 arch_cpu_init(); 122 get_clocks(); 123 mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, 124 CONFIG_SPL_RELOC_MALLOC_SIZE); 125 gd->flags |= GD_FLG_FULL_MALLOC_INIT; 126 127 #ifdef CONFIG_SPL_NAND_BOOT 128 nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, 129 (uchar *)CONFIG_ENV_ADDR); 130 #endif 131 #ifdef CONFIG_SPL_MMC_BOOT 132 mmc_initialize(bd); 133 mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, 134 (uchar *)CONFIG_ENV_ADDR); 135 #endif 136 #ifdef CONFIG_SPL_SPI_BOOT 137 fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, 138 (uchar *)CONFIG_ENV_ADDR); 139 #endif 140 141 gd->env_addr = (ulong)(CONFIG_ENV_ADDR); 142 gd->env_valid = ENV_VALID; 143 144 i2c_init_all(); 145 146 dram_init(); 147 148 #ifdef CONFIG_SPL_MMC_BOOT 149 mmc_boot(); 150 #elif defined(CONFIG_SPL_SPI_BOOT) 151 fsl_spi_boot(); 152 #elif defined(CONFIG_SPL_NAND_BOOT) 153 nand_boot(); 154 #endif 155 } 156