1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright 2014 Freescale Semiconductor, Inc. 3 */ 4 5 #include <common.h> 6 #include <console.h> 7 #include <environment.h> 8 #include <malloc.h> 9 #include <ns16550.h> 10 #include <nand.h> 11 #include <i2c.h> 12 #include <mmc.h> 13 #include <fsl_esdhc.h> 14 #include <spi_flash.h> 15 #include "../common/qixis.h" 16 #include "t102xqds_qixis.h" 17 #include "../common/spl.h" 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 phys_size_t get_effective_memsize(void) 22 { 23 return CONFIG_SYS_L3_SIZE; 24 } 25 26 unsigned long get_board_sys_clk(void) 27 { 28 u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 29 30 switch (sysclk_conf & 0x0F) { 31 case QIXIS_SYSCLK_83: 32 return 83333333; 33 case QIXIS_SYSCLK_100: 34 return 100000000; 35 case QIXIS_SYSCLK_125: 36 return 125000000; 37 case QIXIS_SYSCLK_133: 38 return 133333333; 39 case QIXIS_SYSCLK_150: 40 return 150000000; 41 case QIXIS_SYSCLK_160: 42 return 160000000; 43 case QIXIS_SYSCLK_166: 44 return 166666666; 45 } 46 return 66666666; 47 } 48 49 unsigned long get_board_ddr_clk(void) 50 { 51 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 52 53 switch ((ddrclk_conf & 0x30) >> 4) { 54 case QIXIS_DDRCLK_100: 55 return 100000000; 56 case QIXIS_DDRCLK_125: 57 return 125000000; 58 case QIXIS_DDRCLK_133: 59 return 133333333; 60 } 61 return 66666666; 62 } 63 64 void board_init_f(ulong bootflag) 65 { 66 u32 plat_ratio, sys_clk, ccb_clk; 67 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 68 69 #if defined(CONFIG_ARCH_T1040) && defined(CONFIG_SPL_NAND_BOOT) 70 /* 71 * There is T1040 SoC issue where NOR, FPGA are inaccessible during 72 * NAND boot because IFC signals > IFC_AD7 are not enabled. 73 * This workaround changes RCW source to make all signals enabled. 74 */ 75 u32 porsr1, pinctl; 76 #define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000 77 78 porsr1 = in_be32(&gur->porsr1); 79 pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000); 80 out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl); 81 #endif 82 83 /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ 84 memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); 85 86 /* Update GD pointer */ 87 gd = (gd_t *)(CONFIG_SPL_GD_ADDR); 88 89 console_init_f(); 90 91 /* initialize selected port with appropriate baud rate */ 92 sys_clk = get_board_sys_clk(); 93 plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; 94 ccb_clk = sys_clk * plat_ratio / 2; 95 96 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, 97 ccb_clk / 16 / CONFIG_BAUDRATE); 98 99 #if defined(CONFIG_SPL_MMC_BOOT) 100 puts("\nSD boot...\n"); 101 #elif defined(CONFIG_SPL_SPI_BOOT) 102 puts("\nSPI boot...\n"); 103 #elif defined(CONFIG_SPL_NAND_BOOT) 104 puts("\nNAND boot...\n"); 105 #endif 106 107 relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); 108 } 109 110 void board_init_r(gd_t *gd, ulong dest_addr) 111 { 112 bd_t *bd; 113 114 bd = (bd_t *)(gd + sizeof(gd_t)); 115 memset(bd, 0, sizeof(bd_t)); 116 gd->bd = bd; 117 bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; 118 bd->bi_memsize = CONFIG_SYS_L3_SIZE; 119 120 arch_cpu_init(); 121 get_clocks(); 122 mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, 123 CONFIG_SPL_RELOC_MALLOC_SIZE); 124 gd->flags |= GD_FLG_FULL_MALLOC_INIT; 125 126 #ifdef CONFIG_SPL_NAND_BOOT 127 nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, 128 (uchar *)CONFIG_ENV_ADDR); 129 #endif 130 #ifdef CONFIG_SPL_MMC_BOOT 131 mmc_initialize(bd); 132 mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, 133 (uchar *)CONFIG_ENV_ADDR); 134 #endif 135 #ifdef CONFIG_SPL_SPI_BOOT 136 fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, 137 (uchar *)CONFIG_ENV_ADDR); 138 #endif 139 140 gd->env_addr = (ulong)(CONFIG_ENV_ADDR); 141 gd->env_valid = ENV_VALID; 142 143 i2c_init_all(); 144 145 dram_init(); 146 147 #ifdef CONFIG_SPL_MMC_BOOT 148 mmc_boot(); 149 #elif defined(CONFIG_SPL_SPI_BOOT) 150 fsl_spi_boot(); 151 #elif defined(CONFIG_SPL_NAND_BOOT) 152 nand_boot(); 153 #endif 154 } 155