1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 */ 5 6 #include <common.h> 7 #include <i2c.h> 8 #include <hwconfig.h> 9 #include <asm/mmu.h> 10 #include <fsl_ddr_sdram.h> 11 #include <fsl_ddr_dimm_params.h> 12 #include <asm/fsl_law.h> 13 #include <asm/mpc85xx_gpio.h> 14 15 DECLARE_GLOBAL_DATA_PTR; 16 17 struct board_specific_parameters { 18 u32 n_ranks; 19 u32 datarate_mhz_high; 20 u32 rank_gb; 21 u32 clk_adjust; 22 u32 wrlvl_start; 23 u32 wrlvl_ctl_2; 24 u32 wrlvl_ctl_3; 25 }; 26 27 /* 28 * datarate_mhz_high values need to be in ascending order 29 */ 30 static const struct board_specific_parameters udimm0[] = { 31 /* 32 * memory controller 0 33 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | 34 * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | 35 */ 36 #if defined(CONFIG_SYS_FSL_DDR4) 37 {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, 38 {2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,}, 39 {1, 1666, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, 40 {1, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,}, 41 {1, 2200, 0, 8, 7, 0x08090A0D, 0x0F0F100C,}, 42 #elif defined(CONFIG_SYS_FSL_DDR3) 43 {2, 833, 0, 8, 6, 0x06060607, 0x08080807,}, 44 {2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,}, 45 {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, 46 {1, 833, 0, 8, 6, 0x06060607, 0x08080807,}, 47 {1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,}, 48 {1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, 49 #else 50 #error DDR type not defined 51 #endif 52 {} 53 }; 54 55 static const struct board_specific_parameters *udimms[] = { 56 udimm0, 57 }; 58 59 void fsl_ddr_board_options(memctl_options_t *popts, 60 dimm_params_t *pdimm, 61 unsigned int ctrl_num) 62 { 63 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; 64 ulong ddr_freq; 65 struct cpu_type *cpu = gd->arch.cpu; 66 67 if (ctrl_num > 2) { 68 printf("Not supported controller number %d\n", ctrl_num); 69 return; 70 } 71 if (!pdimm->n_ranks) 72 return; 73 74 pbsp = udimms[0]; 75 76 /* Get clk_adjust according to the board ddr freqency and n_banks 77 * specified in board_specific_parameters table. 78 */ 79 ddr_freq = get_ddr_freq(0) / 1000000; 80 while (pbsp->datarate_mhz_high) { 81 if (pbsp->n_ranks == pdimm->n_ranks && 82 (pdimm->rank_density >> 30) >= pbsp->rank_gb) { 83 if (ddr_freq <= pbsp->datarate_mhz_high) { 84 popts->clk_adjust = pbsp->clk_adjust; 85 popts->wrlvl_start = pbsp->wrlvl_start; 86 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; 87 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; 88 goto found; 89 } 90 pbsp_highest = pbsp; 91 } 92 pbsp++; 93 } 94 95 if (pbsp_highest) { 96 printf("Error: board specific timing not found\n"); 97 printf("for data rate %lu MT/s\n", ddr_freq); 98 printf("Trying to use the highest speed (%u) parameters\n", 99 pbsp_highest->datarate_mhz_high); 100 popts->clk_adjust = pbsp_highest->clk_adjust; 101 popts->wrlvl_start = pbsp_highest->wrlvl_start; 102 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; 103 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; 104 } else { 105 panic("DIMM is not supported by this board"); 106 } 107 found: 108 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", 109 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); 110 debug("\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, ", 111 pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2); 112 debug("wrlvl_ctrl_3 0x%x\n", pbsp->wrlvl_ctl_3); 113 114 /* 115 * Factors to consider for half-strength driver enable: 116 * - number of DIMMs installed 117 */ 118 popts->half_strength_driver_enable = 1; 119 /* 120 * Write leveling override 121 */ 122 popts->wrlvl_override = 1; 123 popts->wrlvl_sample = 0xf; 124 125 /* 126 * rtt and rtt_wr override 127 */ 128 popts->rtt_override = 0; 129 130 /* Enable ZQ calibration */ 131 popts->zq_en = 1; 132 133 /* DHC_EN =1, ODT = 75 Ohm */ 134 #ifdef CONFIG_SYS_FSL_DDR4 135 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); 136 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | 137 DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ 138 #else 139 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); 140 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); 141 142 /* optimize cpo for erratum A-009942 */ 143 popts->cpo_sample = 0x5f; 144 #endif 145 146 /* T1023 supports max DDR bus 32bit width, T1024 supports DDR 64bit, 147 * set DDR bus width to 32bit for T1023 148 */ 149 if (cpu->soc_ver == SVR_T1023) 150 popts->data_bus_width = DDR_DATA_BUS_WIDTH_32; 151 152 #ifdef CONFIG_FORCE_DDR_DATA_BUS_WIDTH_32 153 /* for DDR bus 32bit test on T1024 */ 154 popts->data_bus_width = DDR_DATA_BUS_WIDTH_32; 155 #endif 156 } 157 158 #if defined(CONFIG_DEEP_SLEEP) 159 void board_mem_sleep_setup(void) 160 { 161 void __iomem *qixis_base = (void *)QIXIS_BASE; 162 163 /* does not provide HW signals for power management */ 164 clrbits_8(qixis_base + 0x21, 0x2); 165 /* Disable MCKE isolation */ 166 gpio_set_value(2, 0); 167 udelay(1); 168 } 169 #endif 170 171 int dram_init(void) 172 { 173 phys_size_t dram_size; 174 175 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) 176 puts("Initializing....using SPD\n"); 177 dram_size = fsl_ddr_sdram(); 178 #else 179 /* DDR has been initialised by first stage boot loader */ 180 dram_size = fsl_ddr_sdram_size(); 181 #endif 182 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 183 dram_size *= 0x100000; 184 185 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) 186 fsl_dp_resume(); 187 #endif 188 189 gd->ram_size = dram_size; 190 191 return 0; 192 } 193