1T1024 SoC Overview 2------------------ 3The T1024/T1023 dual core and T1014/T1013 single core QorIQ communication processor 4combines two or one 64-bit Power Architecture e5500 core respectively with high 5performance datapath acceleration logic, and network peripheral bus interfaces 6required for networking and telecommunications. This processor can be used in 7applications such as enterprise WLAN access points, routers, switches, firewall 8and other packet processing intensive small enterprise and branch office appliances, 9and general-purpose embedded computing. Its high level of integration offers 10significant performance benefits and greatly helps to simplify board design. 11 12 13The T1024 SoC includes the following function and features: 14- two e5500 cores, each with a private 256 KB L2 cache 15 - Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant) 16 - Three levels of instructions: User, supervisor, and hypervisor 17 - Independent boot and reset 18 - Secure boot capability 19- 256 KB shared L3 CoreNet platform cache (CPC) 20- Interconnect CoreNet platform 21 - CoreNet coherency manager supporting coherent and noncoherent transactions 22 with prioritization and bandwidth allocation amongst CoreNet endpoints 23 - 150 Gbps coherent read bandwidth 24- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support 25- Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: 26 - Packet parsing, classification, and distribution 27 - Queue management for scheduling, packet sequencing, and congestion management 28 - Cryptography Acceleration (SEC 5.x) 29 - IEEE 1588 support 30 - Hardware buffer management for buffer allocation and deallocation 31 - MACSEC on DPAA-based Ethernet ports 32- Ethernet interfaces 33 - Four 1 Gbps Ethernet controllers 34- Parallel Ethernet interfaces 35 - Two RGMII interfaces 36- High speed peripheral interfaces 37 - Three PCI Express 2.0 controllers/ports running at up to 5 GHz 38 - One SATA controller supporting 1.5 and 3.0 Gb/s operation 39 - One QSGMII interface 40 - Four SGMII interface supporting 1000 Mbps 41 - Three SGMII interfaces supporting up to 2500 Mbps 42 - 10GbE XFI or 10Base-KR interface 43- Additional peripheral interfaces 44 - Two USB 2.0 controllers with integrated PHY 45 - SD/eSDHC/eMMC 46 - eSPI controller 47 - Four I2C controllers 48 - Four UARTs 49 - Four GPIO controllers 50 - Integrated flash controller (IFC) 51 - LCD interface (DIU) with 12 bit dual data rate 52- Multicore programmable interrupt controller (PIC) 53- Two 8-channel DMA engines 54- Single source clocking implementation 55- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) 56- QUICC Engine block 57 - 32-bit RISC controller for flexible support of the communications peripherals 58 - Serial DMA channel for receive and transmit on all serial channels 59 - Two universal communication controllers, supporting TDM, HDLC, and UART 60 61T1023 Personality 62------------------ 63T1023 is a reduced personality of T1024 without QUICC Engine, DIU, and 64unavailable deep sleep. Rest of the blocks are almost same as T1024. 65Differences between T1024 and T1023 66Feature T1024 T1023 67QUICC Engine: yes no 68DIU: yes no 69Deep Sleep: yes no 70I2C controller: 4 3 71DDR: 64-bit 32-bit 72IFC: 32-bit 28-bit 73 74 75T1024QDS board Overview 76----------------------- 77- SERDES Connections 78 4 lanes supporting the following: 79 - PCI Express: supports Gen 1 and Gen 2 80 - SGMII 1G and SGMII 2.5G 81 - QSGMII 82 - XFI 83 - SATA 2.0 84 - High-speed multiplexers route the SerDes traffic to appropriate slots or connectors. 85 - Aurora debug with dedicated connectors. 86- DDR Controller 87 - Supports up to 1600 MTPS data-rate. 88 - Supports one DDR4 or DDR3L module using DDR4 to DDR3L adapter card. 89 - Supports Single-, dual- or quad-rank DIMMs 90 - DDR power supplies 1.35V (DDR3L)/1.20V (DDR4) to all devices with automatic tracking of VTT. 91- IFC/Local Bus 92 - NAND Flash: 8-bit, async, up to 2GB 93 - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB 94 - NOR devices support 8 virtual banks 95 - Socketed to allow alternate devices 96 - GASIC: Simple (minimal) target within QIXIS FPGA 97 - PromJET rapid memory download support 98 - IFC Debug/Development card 99- Ethernet 100 - Two on-board RGMII 10M/100M/1G ethernet ports. 101 - One QSGMII interface 102 - Four SGMII interface supporting 1Gbps 103 - Three SGMII interfaces supporting 2.5Gbps 104 - one 10Gbps XFI or 10Base-KR interface 105- QIXIS System Logic FPGA 106 - Manages system power and reset sequencing. 107 - Manages the configurations of DUT, board, and clock for dynamic shmoo. 108 - Collects V-I-T data in background for code/power profiling. 109 - Supports legacy TMT test features (POSt, IRS, SYSCLK-synchronous assertion). 110 - General fault monitoring and logging. 111 - Powered from ATX 'standby' power supply that allows continuous operation while rest of the system is off. 112- Clocks 113 - System and DDR clock (SYSCLK, DDRCLK). 114 - Switch selectable to one of 16 common settings in the interval of 64 MHz-166 MHz. 115 - Software programmable in 1 MHz increments from 1-200 MHz. 116 - SERDES clocks 117 - Provides clocks to SerDes blocks and slots. 118 - 100 MHz, 125 MHz and 156.25 MHz options. 119 - Spread-spectrum option for 100 MHz. 120- Power Supplies 121 - Dedicated PMBus regulator for VDD and VDDC. 122 - Adjustable from 0.7V to 1.3V at 35A 123 - VDD can be disabled independanty from VDDC for “deep sleep”. 124 - DDR3L/DDR4 power supply for GVDD: 1.35 or 1.20V at up to 22A. 125 - VTT/MVREF automatically track operating voltage. 126 - Dedicated 2.5V VPP supply. 127 - Dedicated regulators/filters for AVDD supplies. 128 - Dedicated regulators for other supplies, for example OVDD, CVDD, DVDD, LVDD, POVDD, and EVDD. 129- Video 130 - DIU supports video up to 1280x1024x32 bpp. 131 - Chrontel CH7201 for HDMI connection. 132 - TI DS90C387R for direct LCD connection. 133 - Raw (not encoded) video connector for testing or other encoders. 134- USB 135 - Supports two USB 2.0 ports with integrated PHYs. 136 - Two type A ports with 5V@1.5A per port. 137 - Second port can be converted to OTG mini-AB. 138- SDHC 139 For T1024QDS, the SDHC port connects directly to an adapter card slot that has the following features: 140 - upport for optional clock feedback paths. 141 - Support for optional high-speed voltage translation direction controls. 142 - Support for SD slots for: SD, SDHC (1x, 4x, 8x) and MMC. 143 - Support for eMMC memory devices. 144- SPI 145 -On-board support of 3 different devices and sizes. 146- Other IO 147 - Two Serial ports 148 - ProfiBus port 149 - Four I2C ports 150 151 152Memory map on T1024QDS 153---------------------- 154Start Address End Address Description Size 1550xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4KB 1560xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB 1570xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB 1580xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB 1590xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB 1600xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB 1610xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB 1620xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB 1630xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB 1640xF_E000_0000 0xF_E7FF_FFFF Promjet 128MB 1650xF_0000_0000 0xF_003F_FFFF DCSR 4MB 1660xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB 1670xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB 1680xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB 1690x0_0000_0000 0x0_ffff_ffff DDR 4GB 170 171 172128MB NOR Flash memory Map 173-------------------------- 174Start Address End Address Definition Max size 1750xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB 1760xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB 1770xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB 1780xEFE00000 0xEFE3FFFF QE firmware (current bank) 256KB 1790xED300000 0xEFEFFFFF rootfs (alt bank) 44MB 1800xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB 1810xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB 1820xEC000000 0xEC01FFFF RCW (alt bank) 128KB 1830xEBF40000 0xEBFFFFFF U-Boot (alt bank) 768KB 1840xEBF20000 0xEBF3FFFF U-Boot env (alt bank) 128KB 1850xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB 1860xEBE00000 0xEBE3FFFF QE firmware (alt bank) 256KB 1870xE9300000 0xEBEFFFFF rootfs (current bank) 44MB 1880xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB 1890xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB 1900xE8000000 0xE801FFFF RCW (current bank) 128KB 191 192 193SerDes clock vs DIP-switch settings 194----------------------------------- 195SRDS_PRTCL_S1 SD1_REF_CLK1 SD1_REF_CLK2 SW4[1:4] 1960x6F 100MHz 125MHz 1101 1970xD6 100MHz 100MHz 1111 1980x99 156.25MHz 100MHz 1011 199 200 201T1024 Clock frequency 202---------------------- 203BIN Core DDR Platform FMan 204Bin1: 1400MHz 1600MT/s 400MHz 700MHz 205Bin2: 1200MHz 1600MT/s 400MHz 600MHz 206Bin3: 1000MHz 1600MT/s 400MHz 500MHz 207 208 209 210Software configurations and board settings 211------------------------------------------ 2121. NOR boot: 213 a. build NOR boot image 214 $ make T1024QDS_defconfig (For DDR3L, by default) 215 or make T1024QDS_D4_defconfig (For DDR4) 216 $ make 217 b. program u-boot.bin image to NOR flash 218 => tftp 1000000 u-boot.bin 219 => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize 220 set SW1[1:8] = '00010011', SW2[1] = '1', SW6[1:4] = '0000' for NOR boot 221 222 Switching between default bank0 and alternate bank4 on NOR flash 223 To change boot source to vbank4: 224 via software: run command 'qixis_reset altbank' in U-Boot. 225 via DIP-switch: set SW6[1:4] = '0100' 226 227 To change boot source to vbank0: 228 via software: run command 'qixis_reset' in U-Boot. 229 via DIP-Switch: set SW6[1:4] = '0000' 230 2312. NAND Boot: 232 a. build PBL image for NAND boot 233 $ make T1024QDS_NAND_defconfig 234 $ make 235 b. program u-boot-with-spl-pbl.bin to NAND flash 236 => tftp 1000000 u-boot-with-spl-pbl.bin 237 => nand erase 0 $filesize 238 => nand write 1000000 0 $filesize 239 set SW1[1:8] = '10000010', SW2[1] = '0' and SW6[1:4] = '1001' for NAND boot 240 2413. SPI Boot: 242 a. build PBL image for SPI boot 243 $ make T1024QDS_SPIFLASH_defconfig 244 $ make 245 b. program u-boot-with-spl-pbl.bin to SPI flash 246 => tftp 1000000 u-boot-with-spl-pbl.bin 247 => sf probe 0 248 => sf erase 0 f0000 249 => sf write 1000000 0 $filesize 250 set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot 251 2524. SD Boot: 253 a. build PBL image for SD boot 254 $ make T1024QDS_SDCARD_defconfig 255 $ make 256 b. program u-boot-with-spl-pbl.bin to SD/MMC card 257 => tftp 1000000 u-boot-with-spl-pbl.bin 258 => mmc write 1000000 8 0x800 259 => tftp 1000000 fsl_fman_ucode_t1024_xx.bin 260 => mmc write 1000000 0x820 80 261 set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot 262 263 264DIU/QE-TDM/SDXC settings 265------------------- 266a) For TDM Riser: set pin_mux=tdm in hwconfig 267b) For UCC(ProfiBus): set pin_mux=ucc in hwconfig 268c) For HDMI(DVI): set pin_mux=hdmi in hwconfig 269d) For LCD(DFP): set pin_mux=lcd in hwconfig 270e) For SDXC: set adaptor=sdxc in hwconfig 271 2722-stage NAND/SPI/SD boot loader 273------------------------------- 274PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM. 275SPL further initializes DDR using SPD and environment variables 276and copy U-Boot(768 KB) from NAND/SPI/SD device to DDR. 277Finally SPL transers control to U-Boot for futher booting. 278 279SPL has following features: 280 - Executes within 256K 281 - No relocation required 282 283Run time view of SPL framework 284------------------------------------------------- 285|Area | Address | 286------------------------------------------------- 287|SecureBoot header | 0xFFFC0000 (32KB) | 288------------------------------------------------- 289|GD, BD | 0xFFFC8000 (4KB) | 290------------------------------------------------- 291|ENV | 0xFFFC9000 (8KB) | 292------------------------------------------------- 293|HEAP | 0xFFFCB000 (30KB) | 294------------------------------------------------- 295|STACK | 0xFFFD8000 (22KB) | 296------------------------------------------------- 297|U-Boot SPL | 0xFFFD8000 (160KB) | 298------------------------------------------------- 299 300NAND Flash memory Map on T1024QDS 301------------------------------------------------------------- 302Start End Definition Size 3030x000000 0x0FFFFF U-Boot 1MB 3040x100000 0x15FFFF U-Boot env 8KB 3050x160000 0x17FFFF FMAN Ucode 128KB 3060x180000 0x19FFFF QE Firmware 128KB 307 308 309SD Card memory Map on T1024QDS 310---------------------------------------------------- 311Block #blocks Definition Size 3120x008 2048 U-Boot img 1MB 3130x800 0016 U-Boot env 8KB 3140x820 0256 FMAN Ucode 128KB 3150x920 0256 QE Firmware 128KB 316 317 318SPI Flash memory Map on T1024QDS 319---------------------------------------------------- 320Start End Definition Size 3210x000000 0x0FFFFF U-Boot img 1MB 3220x100000 0x101FFF U-Boot env 8KB 3230x110000 0x12FFFF FMAN Ucode 128KB 3240x130000 0x14FFFF QE Firmware 128KB 325 326 327For more details, please refer to T1024QDS Reference Manual and access 328website www.freescale.com and Freescale QorIQ SDK Infocenter document. 329