1 /* 2 * (C) Copyright 2013-2015, Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <asm/arch/imx-regs.h> 10 #include <asm/arch/siul.h> 11 #include <asm/arch/lpddr2.h> 12 #include <asm/arch/clock.h> 13 #include <mmc.h> 14 #include <fsl_esdhc.h> 15 #include <miiphy.h> 16 #include <netdev.h> 17 #include <i2c.h> 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 void setup_iomux_ddr(void) 22 { 23 lpddr2_config_iomux(DDR0); 24 lpddr2_config_iomux(DDR1); 25 26 } 27 28 void ddr_phy_init(void) 29 { 30 } 31 32 void ddr_ctrl_init(void) 33 { 34 config_mmdc(0); 35 config_mmdc(1); 36 } 37 38 int dram_init(void) 39 { 40 setup_iomux_ddr(); 41 42 ddr_ctrl_init(); 43 44 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); 45 46 return 0; 47 } 48 49 static void setup_iomux_uart(void) 50 { 51 /* Muxing for linflex */ 52 /* Replace the magic values after bringup */ 53 54 /* set TXD - MSCR[12] PA12 */ 55 writel(SIUL2_UART_TXD, SIUL2_MSCRn(SIUL2_UART0_TXD_PAD)); 56 57 /* set RXD - MSCR[11] - PA11 */ 58 writel(SIUL2_UART_MSCR_RXD, SIUL2_MSCRn(SIUL2_UART0_MSCR_RXD_PAD)); 59 60 /* set RXD - IMCR[200] - 200 */ 61 writel(SIUL2_UART_IMCR_RXD, SIUL2_IMCRn(SIUL2_UART0_IMCR_RXD_PAD)); 62 } 63 64 static void setup_iomux_enet(void) 65 { 66 } 67 68 static void setup_iomux_i2c(void) 69 { 70 } 71 72 #ifdef CONFIG_SYS_USE_NAND 73 void setup_iomux_nfc(void) 74 { 75 } 76 #endif 77 78 #ifdef CONFIG_FSL_ESDHC 79 struct fsl_esdhc_cfg esdhc_cfg[1] = { 80 {USDHC_BASE_ADDR}, 81 }; 82 83 int board_mmc_getcd(struct mmc *mmc) 84 { 85 /* eSDHC1 is always present */ 86 return 1; 87 } 88 89 int board_mmc_init(bd_t * bis) 90 { 91 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_USDHC_CLK); 92 93 /* Set iomux PADS for USDHC */ 94 95 /* PK6 pad: uSDHC clk */ 96 writel(SIUL2_USDHC_PAD_CTRL_CLK, SIUL2_MSCRn(150)); 97 writel(0x3, SIUL2_MSCRn(902)); 98 99 /* PK7 pad: uSDHC CMD */ 100 writel(SIUL2_USDHC_PAD_CTRL_CMD, SIUL2_MSCRn(151)); 101 writel(0x3, SIUL2_MSCRn(901)); 102 103 /* PK8 pad: uSDHC DAT0 */ 104 writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(152)); 105 writel(0x3, SIUL2_MSCRn(903)); 106 107 /* PK9 pad: uSDHC DAT1 */ 108 writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(153)); 109 writel(0x3, SIUL2_MSCRn(904)); 110 111 /* PK10 pad: uSDHC DAT2 */ 112 writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(154)); 113 writel(0x3, SIUL2_MSCRn(905)); 114 115 /* PK11 pad: uSDHC DAT3 */ 116 writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(155)); 117 writel(0x3, SIUL2_MSCRn(906)); 118 119 /* PK15 pad: uSDHC DAT4 */ 120 writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(159)); 121 writel(0x3, SIUL2_MSCRn(907)); 122 123 /* PL0 pad: uSDHC DAT5 */ 124 writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(160)); 125 writel(0x3, SIUL2_MSCRn(908)); 126 127 /* PL1 pad: uSDHC DAT6 */ 128 writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(161)); 129 writel(0x3, SIUL2_MSCRn(909)); 130 131 /* PL2 pad: uSDHC DAT7 */ 132 writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(162)); 133 writel(0x3, SIUL2_MSCRn(910)); 134 135 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); 136 } 137 #endif 138 139 static void mscm_init(void) 140 { 141 struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_BASE_ADDR; 142 int i; 143 144 for (i = 0; i < MSCM_IRSPRC_NUM; i++) 145 writew(MSCM_IRSPRC_CPn_EN, &mscmir->irsprc[i]); 146 } 147 148 int board_phy_config(struct phy_device *phydev) 149 { 150 if (phydev->drv->config) 151 phydev->drv->config(phydev); 152 153 return 0; 154 } 155 156 int board_early_init_f(void) 157 { 158 clock_init(); 159 mscm_init(); 160 161 setup_iomux_uart(); 162 setup_iomux_enet(); 163 setup_iomux_i2c(); 164 #ifdef CONFIG_SYS_USE_NAND 165 setup_iomux_nfc(); 166 #endif 167 return 0; 168 } 169 170 int board_init(void) 171 { 172 /* address of boot parameters */ 173 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 174 175 return 0; 176 } 177 178 int checkboard(void) 179 { 180 puts("Board: s32v234evb\n"); 181 182 return 0; 183 } 184