1*9702ec00SEddy Petrișor /* 2*9702ec00SEddy Petrișor * (C) Copyright 2015, Freescale Semiconductor, Inc. 3*9702ec00SEddy Petrișor * 4*9702ec00SEddy Petrișor * SPDX-License-Identifier: GPL-2.0+ 5*9702ec00SEddy Petrișor */ 6*9702ec00SEddy Petrișor 7*9702ec00SEddy Petrișor #include <asm/io.h> 8*9702ec00SEddy Petrișor #include <asm/arch/imx-regs.h> 9*9702ec00SEddy Petrișor #include <asm/arch/siul.h> 10*9702ec00SEddy Petrișor #include <asm/arch/lpddr2.h> 11*9702ec00SEddy Petrișor #include <asm/arch/mmdc.h> 12*9702ec00SEddy Petrișor 13*9702ec00SEddy Petrișor volatile int mscr_offset_ck0; 14*9702ec00SEddy Petrișor 15*9702ec00SEddy Petrișor void lpddr2_config_iomux(uint8_t module) 16*9702ec00SEddy Petrișor { 17*9702ec00SEddy Petrișor int i; 18*9702ec00SEddy Petrișor 19*9702ec00SEddy Petrișor switch (module) { 20*9702ec00SEddy Petrișor case DDR0: 21*9702ec00SEddy Petrișor mscr_offset_ck0 = SIUL2_MSCRn(_DDR0_CKE0); 22*9702ec00SEddy Petrișor writel(LPDDR2_CLK0_PAD, SIUL2_MSCRn(_DDR0_CLK0)); 23*9702ec00SEddy Petrișor 24*9702ec00SEddy Petrișor writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR0_CKE0)); 25*9702ec00SEddy Petrișor writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR0_CKE1)); 26*9702ec00SEddy Petrișor 27*9702ec00SEddy Petrișor writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR0_CS_B0)); 28*9702ec00SEddy Petrișor writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR0_CS_B1)); 29*9702ec00SEddy Petrișor 30*9702ec00SEddy Petrișor for (i = _DDR0_DM0; i <= _DDR0_DM3; i++) 31*9702ec00SEddy Petrișor writel(LPDDR2_DMn_PAD, SIUL2_MSCRn(i)); 32*9702ec00SEddy Petrișor 33*9702ec00SEddy Petrișor for (i = _DDR0_DQS0; i <= _DDR0_DQS3; i++) 34*9702ec00SEddy Petrișor writel(LPDDR2_DQSn_PAD, SIUL2_MSCRn(i)); 35*9702ec00SEddy Petrișor 36*9702ec00SEddy Petrișor for (i = _DDR0_A0; i <= _DDR0_A9; i++) 37*9702ec00SEddy Petrișor writel(LPDDR2_An_PAD, SIUL2_MSCRn(i)); 38*9702ec00SEddy Petrișor 39*9702ec00SEddy Petrișor for (i = _DDR0_D0; i <= _DDR0_D31; i++) 40*9702ec00SEddy Petrișor writel(LPDDR2_Dn_PAD, SIUL2_MSCRn(i)); 41*9702ec00SEddy Petrișor break; 42*9702ec00SEddy Petrișor case DDR1: 43*9702ec00SEddy Petrișor writel(LPDDR2_CLK0_PAD, SIUL2_MSCRn(_DDR1_CLK0)); 44*9702ec00SEddy Petrișor 45*9702ec00SEddy Petrișor writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR1_CKE0)); 46*9702ec00SEddy Petrișor writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR1_CKE1)); 47*9702ec00SEddy Petrișor 48*9702ec00SEddy Petrișor writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR1_CS_B0)); 49*9702ec00SEddy Petrișor writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR1_CS_B1)); 50*9702ec00SEddy Petrișor 51*9702ec00SEddy Petrișor for (i = _DDR1_DM0; i <= _DDR1_DM3; i++) 52*9702ec00SEddy Petrișor writel(LPDDR2_DMn_PAD, SIUL2_MSCRn(i)); 53*9702ec00SEddy Petrișor 54*9702ec00SEddy Petrișor for (i = _DDR1_DQS0; i <= _DDR1_DQS3; i++) 55*9702ec00SEddy Petrișor writel(LPDDR2_DQSn_PAD, SIUL2_MSCRn(i)); 56*9702ec00SEddy Petrișor 57*9702ec00SEddy Petrișor for (i = _DDR1_A0; i <= _DDR1_A9; i++) 58*9702ec00SEddy Petrișor writel(LPDDR2_An_PAD, SIUL2_MSCRn(i)); 59*9702ec00SEddy Petrișor 60*9702ec00SEddy Petrișor for (i = _DDR1_D0; i <= _DDR1_D31; i++) 61*9702ec00SEddy Petrișor writel(LPDDR2_Dn_PAD, SIUL2_MSCRn(i)); 62*9702ec00SEddy Petrișor break; 63*9702ec00SEddy Petrișor } 64*9702ec00SEddy Petrișor } 65*9702ec00SEddy Petrișor 66*9702ec00SEddy Petrișor void config_mmdc(uint8_t module) 67*9702ec00SEddy Petrișor { 68*9702ec00SEddy Petrișor unsigned long mmdc_addr = (module) ? MMDC1_BASE_ADDR : MMDC0_BASE_ADDR; 69*9702ec00SEddy Petrișor 70*9702ec00SEddy Petrișor writel(MMDC_MDSCR_CFG_VALUE, mmdc_addr + MMDC_MDSCR); 71*9702ec00SEddy Petrișor 72*9702ec00SEddy Petrișor writel(MMDC_MDCFG0_VALUE, mmdc_addr + MMDC_MDCFG0); 73*9702ec00SEddy Petrișor writel(MMDC_MDCFG1_VALUE, mmdc_addr + MMDC_MDCFG1); 74*9702ec00SEddy Petrișor writel(MMDC_MDCFG2_VALUE, mmdc_addr + MMDC_MDCFG2); 75*9702ec00SEddy Petrișor writel(MMDC_MDCFG3LP_VALUE, mmdc_addr + MMDC_MDCFG3LP); 76*9702ec00SEddy Petrișor writel(MMDC_MDOTC_VALUE, mmdc_addr + MMDC_MDOTC); 77*9702ec00SEddy Petrișor writel(MMDC_MDMISC_VALUE, mmdc_addr + MMDC_MDMISC); 78*9702ec00SEddy Petrișor writel(MMDC_MDOR_VALUE, mmdc_addr + MMDC_MDOR); 79*9702ec00SEddy Petrișor writel(_MDCTL, mmdc_addr + MMDC_MDCTL); 80*9702ec00SEddy Petrișor 81*9702ec00SEddy Petrișor writel(MMDC_MPMUR0_VALUE, mmdc_addr + MMDC_MPMUR0); 82*9702ec00SEddy Petrișor 83*9702ec00SEddy Petrișor while (readl(mmdc_addr + MMDC_MPMUR0) & MMDC_MPMUR0_FRC_MSR) { 84*9702ec00SEddy Petrișor } 85*9702ec00SEddy Petrișor 86*9702ec00SEddy Petrișor writel(MMDC_MDSCR_RST_VALUE, mmdc_addr + MMDC_MDSCR); 87*9702ec00SEddy Petrișor 88*9702ec00SEddy Petrișor /* Perform ZQ calibration */ 89*9702ec00SEddy Petrișor writel(MMDC_MPZQLP2CTL_VALUE, mmdc_addr + MMDC_MPZQLP2CTL); 90*9702ec00SEddy Petrișor writel(MMDC_MPZQHWCTRL_VALUE, mmdc_addr + MMDC_MPZQHWCTRL); 91*9702ec00SEddy Petrișor while (readl(mmdc_addr + MMDC_MPZQHWCTRL) & MMDC_MPZQHWCTRL_ZQ_HW_FOR) { 92*9702ec00SEddy Petrișor } 93*9702ec00SEddy Petrișor 94*9702ec00SEddy Petrișor /* Enable MMDC with CS0 */ 95*9702ec00SEddy Petrișor writel(_MDCTL + 0x80000000, mmdc_addr + MMDC_MDCTL); 96*9702ec00SEddy Petrișor 97*9702ec00SEddy Petrișor /* Complete the initialization sequence as defined by JEDEC */ 98*9702ec00SEddy Petrișor writel(MMDC_MDSCR_MR1_VALUE, mmdc_addr + MMDC_MDSCR); 99*9702ec00SEddy Petrișor writel(MMDC_MDSCR_MR2_VALUE, mmdc_addr + MMDC_MDSCR); 100*9702ec00SEddy Petrișor writel(MMDC_MDSCR_MR3_VALUE, mmdc_addr + MMDC_MDSCR); 101*9702ec00SEddy Petrișor writel(MMDC_MDSCR_MR10_VALUE, mmdc_addr + MMDC_MDSCR); 102*9702ec00SEddy Petrișor 103*9702ec00SEddy Petrișor /* Set the amount of DRAM */ 104*9702ec00SEddy Petrișor /* Set DQS settings based on board type */ 105*9702ec00SEddy Petrișor 106*9702ec00SEddy Petrișor switch (module) { 107*9702ec00SEddy Petrișor case MMDC0: 108*9702ec00SEddy Petrișor writel(MMDC_MDASP_MODULE0_VALUE, mmdc_addr + MMDC_MDASP); 109*9702ec00SEddy Petrișor writel(MMDC_MPRDDLCTL_MODULE0_VALUE, 110*9702ec00SEddy Petrișor mmdc_addr + MMDC_MPRDDLCTL); 111*9702ec00SEddy Petrișor writel(MMDC_MPWRDLCTL_MODULE0_VALUE, 112*9702ec00SEddy Petrișor mmdc_addr + MMDC_MPWRDLCTL); 113*9702ec00SEddy Petrișor writel(MMDC_MPDGCTRL0_MODULE0_VALUE, 114*9702ec00SEddy Petrișor mmdc_addr + MMDC_MPDGCTRL0); 115*9702ec00SEddy Petrișor writel(MMDC_MPDGCTRL1_MODULE0_VALUE, 116*9702ec00SEddy Petrișor mmdc_addr + MMDC_MPDGCTRL1); 117*9702ec00SEddy Petrișor break; 118*9702ec00SEddy Petrișor case MMDC1: 119*9702ec00SEddy Petrișor writel(MMDC_MDASP_MODULE1_VALUE, mmdc_addr + MMDC_MDASP); 120*9702ec00SEddy Petrișor writel(MMDC_MPRDDLCTL_MODULE1_VALUE, 121*9702ec00SEddy Petrișor mmdc_addr + MMDC_MPRDDLCTL); 122*9702ec00SEddy Petrișor writel(MMDC_MPWRDLCTL_MODULE1_VALUE, 123*9702ec00SEddy Petrișor mmdc_addr + MMDC_MPWRDLCTL); 124*9702ec00SEddy Petrișor writel(MMDC_MPDGCTRL0_MODULE1_VALUE, 125*9702ec00SEddy Petrișor mmdc_addr + MMDC_MPDGCTRL0); 126*9702ec00SEddy Petrișor writel(MMDC_MPDGCTRL1_MODULE1_VALUE, 127*9702ec00SEddy Petrișor mmdc_addr + MMDC_MPDGCTRL1); 128*9702ec00SEddy Petrișor break; 129*9702ec00SEddy Petrișor } 130*9702ec00SEddy Petrișor 131*9702ec00SEddy Petrișor writel(MMDC_MDRWD_VALUE, mmdc_addr + MMDC_MDRWD); 132*9702ec00SEddy Petrișor writel(MMDC_MDPDC_VALUE, mmdc_addr + MMDC_MDPDC); 133*9702ec00SEddy Petrișor writel(MMDC_MDREF_VALUE, mmdc_addr + MMDC_MDREF); 134*9702ec00SEddy Petrișor writel(MMDC_MPODTCTRL_VALUE, mmdc_addr + MMDC_MPODTCTRL); 135*9702ec00SEddy Petrișor writel(MMDC_MDSCR_DEASSERT_VALUE, mmdc_addr + MMDC_MDSCR); 136*9702ec00SEddy Petrișor 137*9702ec00SEddy Petrișor } 138