1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 29702ec00SEddy Petrișor /* 39702ec00SEddy Petrișor * (C) Copyright 2015, Freescale Semiconductor, Inc. 49702ec00SEddy Petrișor */ 59702ec00SEddy Petrișor 69702ec00SEddy Petrișor #include <asm/io.h> 79702ec00SEddy Petrișor #include <asm/arch/imx-regs.h> 89702ec00SEddy Petrișor #include <asm/arch/siul.h> 99702ec00SEddy Petrișor #include <asm/arch/lpddr2.h> 109702ec00SEddy Petrișor #include <asm/arch/mmdc.h> 119702ec00SEddy Petrișor 129702ec00SEddy Petrișor volatile int mscr_offset_ck0; 139702ec00SEddy Petrișor 149702ec00SEddy Petrișor void lpddr2_config_iomux(uint8_t module) 159702ec00SEddy Petrișor { 169702ec00SEddy Petrișor int i; 179702ec00SEddy Petrișor 189702ec00SEddy Petrișor switch (module) { 199702ec00SEddy Petrișor case DDR0: 209702ec00SEddy Petrișor mscr_offset_ck0 = SIUL2_MSCRn(_DDR0_CKE0); 219702ec00SEddy Petrișor writel(LPDDR2_CLK0_PAD, SIUL2_MSCRn(_DDR0_CLK0)); 229702ec00SEddy Petrișor 239702ec00SEddy Petrișor writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR0_CKE0)); 249702ec00SEddy Petrișor writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR0_CKE1)); 259702ec00SEddy Petrișor 269702ec00SEddy Petrișor writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR0_CS_B0)); 279702ec00SEddy Petrișor writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR0_CS_B1)); 289702ec00SEddy Petrișor 299702ec00SEddy Petrișor for (i = _DDR0_DM0; i <= _DDR0_DM3; i++) 309702ec00SEddy Petrișor writel(LPDDR2_DMn_PAD, SIUL2_MSCRn(i)); 319702ec00SEddy Petrișor 329702ec00SEddy Petrișor for (i = _DDR0_DQS0; i <= _DDR0_DQS3; i++) 339702ec00SEddy Petrișor writel(LPDDR2_DQSn_PAD, SIUL2_MSCRn(i)); 349702ec00SEddy Petrișor 359702ec00SEddy Petrișor for (i = _DDR0_A0; i <= _DDR0_A9; i++) 369702ec00SEddy Petrișor writel(LPDDR2_An_PAD, SIUL2_MSCRn(i)); 379702ec00SEddy Petrișor 389702ec00SEddy Petrișor for (i = _DDR0_D0; i <= _DDR0_D31; i++) 399702ec00SEddy Petrișor writel(LPDDR2_Dn_PAD, SIUL2_MSCRn(i)); 409702ec00SEddy Petrișor break; 419702ec00SEddy Petrișor case DDR1: 429702ec00SEddy Petrișor writel(LPDDR2_CLK0_PAD, SIUL2_MSCRn(_DDR1_CLK0)); 439702ec00SEddy Petrișor 449702ec00SEddy Petrișor writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR1_CKE0)); 459702ec00SEddy Petrișor writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR1_CKE1)); 469702ec00SEddy Petrișor 479702ec00SEddy Petrișor writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR1_CS_B0)); 489702ec00SEddy Petrișor writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR1_CS_B1)); 499702ec00SEddy Petrișor 509702ec00SEddy Petrișor for (i = _DDR1_DM0; i <= _DDR1_DM3; i++) 519702ec00SEddy Petrișor writel(LPDDR2_DMn_PAD, SIUL2_MSCRn(i)); 529702ec00SEddy Petrișor 539702ec00SEddy Petrișor for (i = _DDR1_DQS0; i <= _DDR1_DQS3; i++) 549702ec00SEddy Petrișor writel(LPDDR2_DQSn_PAD, SIUL2_MSCRn(i)); 559702ec00SEddy Petrișor 569702ec00SEddy Petrișor for (i = _DDR1_A0; i <= _DDR1_A9; i++) 579702ec00SEddy Petrișor writel(LPDDR2_An_PAD, SIUL2_MSCRn(i)); 589702ec00SEddy Petrișor 599702ec00SEddy Petrișor for (i = _DDR1_D0; i <= _DDR1_D31; i++) 609702ec00SEddy Petrișor writel(LPDDR2_Dn_PAD, SIUL2_MSCRn(i)); 619702ec00SEddy Petrișor break; 629702ec00SEddy Petrișor } 639702ec00SEddy Petrișor } 649702ec00SEddy Petrișor 659702ec00SEddy Petrișor void config_mmdc(uint8_t module) 669702ec00SEddy Petrișor { 679702ec00SEddy Petrișor unsigned long mmdc_addr = (module) ? MMDC1_BASE_ADDR : MMDC0_BASE_ADDR; 689702ec00SEddy Petrișor 699702ec00SEddy Petrișor writel(MMDC_MDSCR_CFG_VALUE, mmdc_addr + MMDC_MDSCR); 709702ec00SEddy Petrișor 719702ec00SEddy Petrișor writel(MMDC_MDCFG0_VALUE, mmdc_addr + MMDC_MDCFG0); 729702ec00SEddy Petrișor writel(MMDC_MDCFG1_VALUE, mmdc_addr + MMDC_MDCFG1); 739702ec00SEddy Petrișor writel(MMDC_MDCFG2_VALUE, mmdc_addr + MMDC_MDCFG2); 749702ec00SEddy Petrișor writel(MMDC_MDCFG3LP_VALUE, mmdc_addr + MMDC_MDCFG3LP); 759702ec00SEddy Petrișor writel(MMDC_MDOTC_VALUE, mmdc_addr + MMDC_MDOTC); 769702ec00SEddy Petrișor writel(MMDC_MDMISC_VALUE, mmdc_addr + MMDC_MDMISC); 779702ec00SEddy Petrișor writel(MMDC_MDOR_VALUE, mmdc_addr + MMDC_MDOR); 789702ec00SEddy Petrișor writel(_MDCTL, mmdc_addr + MMDC_MDCTL); 799702ec00SEddy Petrișor 809702ec00SEddy Petrișor writel(MMDC_MPMUR0_VALUE, mmdc_addr + MMDC_MPMUR0); 819702ec00SEddy Petrișor 829702ec00SEddy Petrișor while (readl(mmdc_addr + MMDC_MPMUR0) & MMDC_MPMUR0_FRC_MSR) { 839702ec00SEddy Petrișor } 849702ec00SEddy Petrișor 859702ec00SEddy Petrișor writel(MMDC_MDSCR_RST_VALUE, mmdc_addr + MMDC_MDSCR); 869702ec00SEddy Petrișor 879702ec00SEddy Petrișor /* Perform ZQ calibration */ 889702ec00SEddy Petrișor writel(MMDC_MPZQLP2CTL_VALUE, mmdc_addr + MMDC_MPZQLP2CTL); 899702ec00SEddy Petrișor writel(MMDC_MPZQHWCTRL_VALUE, mmdc_addr + MMDC_MPZQHWCTRL); 909702ec00SEddy Petrișor while (readl(mmdc_addr + MMDC_MPZQHWCTRL) & MMDC_MPZQHWCTRL_ZQ_HW_FOR) { 919702ec00SEddy Petrișor } 929702ec00SEddy Petrișor 939702ec00SEddy Petrișor /* Enable MMDC with CS0 */ 949702ec00SEddy Petrișor writel(_MDCTL + 0x80000000, mmdc_addr + MMDC_MDCTL); 959702ec00SEddy Petrișor 969702ec00SEddy Petrișor /* Complete the initialization sequence as defined by JEDEC */ 979702ec00SEddy Petrișor writel(MMDC_MDSCR_MR1_VALUE, mmdc_addr + MMDC_MDSCR); 989702ec00SEddy Petrișor writel(MMDC_MDSCR_MR2_VALUE, mmdc_addr + MMDC_MDSCR); 999702ec00SEddy Petrișor writel(MMDC_MDSCR_MR3_VALUE, mmdc_addr + MMDC_MDSCR); 1009702ec00SEddy Petrișor writel(MMDC_MDSCR_MR10_VALUE, mmdc_addr + MMDC_MDSCR); 1019702ec00SEddy Petrișor 1029702ec00SEddy Petrișor /* Set the amount of DRAM */ 1039702ec00SEddy Petrișor /* Set DQS settings based on board type */ 1049702ec00SEddy Petrișor 1059702ec00SEddy Petrișor switch (module) { 1069702ec00SEddy Petrișor case MMDC0: 1079702ec00SEddy Petrișor writel(MMDC_MDASP_MODULE0_VALUE, mmdc_addr + MMDC_MDASP); 1089702ec00SEddy Petrișor writel(MMDC_MPRDDLCTL_MODULE0_VALUE, 1099702ec00SEddy Petrișor mmdc_addr + MMDC_MPRDDLCTL); 1109702ec00SEddy Petrișor writel(MMDC_MPWRDLCTL_MODULE0_VALUE, 1119702ec00SEddy Petrișor mmdc_addr + MMDC_MPWRDLCTL); 1129702ec00SEddy Petrișor writel(MMDC_MPDGCTRL0_MODULE0_VALUE, 1139702ec00SEddy Petrișor mmdc_addr + MMDC_MPDGCTRL0); 1149702ec00SEddy Petrișor writel(MMDC_MPDGCTRL1_MODULE0_VALUE, 1159702ec00SEddy Petrișor mmdc_addr + MMDC_MPDGCTRL1); 1169702ec00SEddy Petrișor break; 1179702ec00SEddy Petrișor case MMDC1: 1189702ec00SEddy Petrișor writel(MMDC_MDASP_MODULE1_VALUE, mmdc_addr + MMDC_MDASP); 1199702ec00SEddy Petrișor writel(MMDC_MPRDDLCTL_MODULE1_VALUE, 1209702ec00SEddy Petrișor mmdc_addr + MMDC_MPRDDLCTL); 1219702ec00SEddy Petrișor writel(MMDC_MPWRDLCTL_MODULE1_VALUE, 1229702ec00SEddy Petrișor mmdc_addr + MMDC_MPWRDLCTL); 1239702ec00SEddy Petrișor writel(MMDC_MPDGCTRL0_MODULE1_VALUE, 1249702ec00SEddy Petrișor mmdc_addr + MMDC_MPDGCTRL0); 1259702ec00SEddy Petrișor writel(MMDC_MPDGCTRL1_MODULE1_VALUE, 1269702ec00SEddy Petrișor mmdc_addr + MMDC_MPDGCTRL1); 1279702ec00SEddy Petrișor break; 1289702ec00SEddy Petrișor } 1299702ec00SEddy Petrișor 1309702ec00SEddy Petrișor writel(MMDC_MDRWD_VALUE, mmdc_addr + MMDC_MDRWD); 1319702ec00SEddy Petrișor writel(MMDC_MDPDC_VALUE, mmdc_addr + MMDC_MDPDC); 1329702ec00SEddy Petrișor writel(MMDC_MDREF_VALUE, mmdc_addr + MMDC_MDREF); 1339702ec00SEddy Petrișor writel(MMDC_MPODTCTRL_VALUE, mmdc_addr + MMDC_MPODTCTRL); 1349702ec00SEddy Petrișor writel(MMDC_MDSCR_DEASSERT_VALUE, mmdc_addr + MMDC_MDSCR); 1359702ec00SEddy Petrișor 1369702ec00SEddy Petrișor } 137