1 /* 2 * Copyright 2011 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <netdev.h> 26 #include <linux/compiler.h> 27 #include <asm/mmu.h> 28 #include <asm/processor.h> 29 #include <asm/cache.h> 30 #include <asm/immap_85xx.h> 31 #include <asm/fsl_law.h> 32 #include <asm/fsl_serdes.h> 33 #include <asm/fsl_portals.h> 34 #include <asm/fsl_liodn.h> 35 #include <fm_eth.h> 36 37 extern void pci_of_setup(void *blob, bd_t *bd); 38 39 #include "cpld.h" 40 41 DECLARE_GLOBAL_DATA_PTR; 42 43 int checkboard(void) 44 { 45 u8 sw; 46 struct cpu_type *cpu = gd->cpu; 47 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 48 unsigned int i; 49 50 printf("Board: %sRDB, ", cpu->name); 51 printf("CPLD version: %d.%d ", CPLD_READ(cpld_ver), 52 CPLD_READ(cpld_ver_sub)); 53 54 sw = CPLD_READ(fbank_sel); 55 printf("vBank: %d\n", sw & 0x1); 56 57 #ifdef CONFIG_PHYS_64BIT 58 puts("36-bit Addressing\n"); 59 #endif 60 61 /* 62 * Display the RCW, so that no one gets confused as to what RCW 63 * we're actually using for this boot. 64 */ 65 puts("Reset Configuration Word (RCW):"); 66 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { 67 u32 rcw = in_be32(&gur->rcwsr[i]); 68 69 if ((i % 4) == 0) 70 printf("\n %08x:", i * 4); 71 printf(" %08x", rcw); 72 } 73 puts("\n"); 74 75 /* 76 * Display the actual SERDES reference clocks as configured by the 77 * dip switches on the board. Note that the SWx registers could 78 * technically be set to force the reference clocks to match the 79 * values that the SERDES expects (or vice versa). For now, however, 80 * we just display both values and hope the user notices when they 81 * don't match. 82 */ 83 puts("SERDES Reference Clocks: "); 84 sw = in_8(&CPLD_SW(2)) >> 2; 85 for (i = 0; i < 2; i++) { 86 static const char * const freq[][3] = {{"0", "100", "125"}, 87 {"100", "156.25", "125"} 88 }; 89 unsigned int clock = (sw >> (2 * i)) & 3; 90 91 printf("Bank%u=%sMhz ", i+1, freq[i][clock]); 92 } 93 puts("\n"); 94 95 return 0; 96 } 97 98 int board_early_init_f(void) 99 { 100 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 101 102 /* board only uses the DDR_MCK0/1, so disable the DDR_MCK2/3 */ 103 setbits_be32(&gur->ddrclkdr, 0x000f000f); 104 105 return 0; 106 } 107 108 int board_early_init_r(void) 109 { 110 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 111 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); 112 113 /* 114 * Remap Boot flash + PROMJET region to caching-inhibited 115 * so that flash can be erased properly. 116 */ 117 118 /* Flush d-cache and invalidate i-cache of any FLASH data */ 119 flush_dcache(); 120 invalidate_icache(); 121 122 /* invalidate existing TLB entry for flash + promjet */ 123 disable_tlb(flash_esel); 124 125 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, 126 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 127 0, flash_esel, BOOKE_PAGESZ_256M, 1); 128 129 set_liodns(); 130 setup_portals(); 131 132 return 0; 133 } 134 135 unsigned long get_board_sys_clk(unsigned long dummy) 136 { 137 u8 sysclk_conf = CPLD_READ(sysclk_sw1); 138 139 switch (sysclk_conf & 0x7) { 140 case CPLD_SYSCLK_83: 141 return 83333333; 142 case CPLD_SYSCLK_100: 143 return 100000000; 144 default: 145 return 66666666; 146 } 147 } 148 149 static const char *serdes_clock_to_string(u32 clock) 150 { 151 switch (clock) { 152 case SRDS_PLLCR0_RFCK_SEL_100: 153 return "100"; 154 case SRDS_PLLCR0_RFCK_SEL_125: 155 return "125"; 156 case SRDS_PLLCR0_RFCK_SEL_156_25: 157 return "156.25"; 158 default: 159 return "150"; 160 } 161 } 162 163 #define NUM_SRDS_BANKS 2 164 165 int misc_init_r(void) 166 { 167 serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 168 u32 actual[NUM_SRDS_BANKS]; 169 unsigned int i; 170 u8 sw; 171 static const int freq[][3] = { 172 {0, SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_125}, 173 {SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_156_25, 174 SRDS_PLLCR0_RFCK_SEL_125} 175 }; 176 177 sw = in_8(&CPLD_SW(2)) >> 2; 178 for (i = 0; i < NUM_SRDS_BANKS; i++) { 179 unsigned int clock = (sw >> (2 * i)) & 3; 180 if (clock == 0x3) { 181 printf("Warning: SDREFCLK%u switch setting of '11' is " 182 "unsupported\n", i + 1); 183 break; 184 } 185 if (i == 0 && clock == 0) 186 puts("Warning: SDREFCLK1 switch setting of" 187 "'00' is unsupported\n"); 188 else 189 actual[i] = freq[i][clock]; 190 } 191 192 for (i = 0; i < NUM_SRDS_BANKS; i++) { 193 u32 expected = in_be32(®s->bank[i].pllcr0); 194 expected &= SRDS_PLLCR0_RFCK_SEL_MASK; 195 if (expected != actual[i]) { 196 printf("Warning: SERDES bank %u expects reference clock" 197 " %sMHz, but actual is %sMHz\n", i + 1, 198 serdes_clock_to_string(expected), 199 serdes_clock_to_string(actual[i])); 200 } 201 } 202 203 return 0; 204 } 205 206 void ft_board_setup(void *blob, bd_t *bd) 207 { 208 phys_addr_t base; 209 phys_size_t size; 210 211 ft_cpu_setup(blob, bd); 212 213 base = getenv_bootm_low(); 214 size = getenv_bootm_size(); 215 216 fdt_fixup_memory(blob, (u64)base, (u64)size); 217 218 #ifdef CONFIG_PCI 219 pci_of_setup(blob, bd); 220 #endif 221 222 fdt_fixup_liodn(blob); 223 #ifdef CONFIG_SYS_DPAA_FMAN 224 fdt_fixup_fman_ethernet(blob); 225 #endif 226 } 227