1 /* 2 * Copyright 2011,2012 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <netdev.h> 26 #include <linux/compiler.h> 27 #include <asm/mmu.h> 28 #include <asm/processor.h> 29 #include <asm/cache.h> 30 #include <asm/immap_85xx.h> 31 #include <asm/fsl_law.h> 32 #include <asm/fsl_serdes.h> 33 #include <asm/fsl_portals.h> 34 #include <asm/fsl_liodn.h> 35 #include <fm_eth.h> 36 37 extern void pci_of_setup(void *blob, bd_t *bd); 38 39 #include "cpld.h" 40 41 DECLARE_GLOBAL_DATA_PTR; 42 43 int checkboard(void) 44 { 45 u8 sw; 46 struct cpu_type *cpu = gd->arch.cpu; 47 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 48 unsigned int i; 49 50 printf("Board: %sRDB, ", cpu->name); 51 printf("CPLD version: %d.%d ", CPLD_READ(cpld_ver), 52 CPLD_READ(cpld_ver_sub)); 53 54 sw = CPLD_READ(fbank_sel); 55 printf("vBank: %d\n", sw & 0x1); 56 57 /* 58 * Display the RCW, so that no one gets confused as to what RCW 59 * we're actually using for this boot. 60 */ 61 puts("Reset Configuration Word (RCW):"); 62 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { 63 u32 rcw = in_be32(&gur->rcwsr[i]); 64 65 if ((i % 4) == 0) 66 printf("\n %08x:", i * 4); 67 printf(" %08x", rcw); 68 } 69 puts("\n"); 70 71 /* 72 * Display the actual SERDES reference clocks as configured by the 73 * dip switches on the board. Note that the SWx registers could 74 * technically be set to force the reference clocks to match the 75 * values that the SERDES expects (or vice versa). For now, however, 76 * we just display both values and hope the user notices when they 77 * don't match. 78 */ 79 puts("SERDES Reference Clocks: "); 80 sw = in_8(&CPLD_SW(2)) >> 2; 81 for (i = 0; i < 2; i++) { 82 static const char * const freq[][3] = {{"0", "100", "125"}, 83 {"100", "156.25", "125"} 84 }; 85 unsigned int clock = (sw >> (2 * i)) & 3; 86 87 printf("Bank%u=%sMhz ", i+1, freq[i][clock]); 88 } 89 puts("\n"); 90 91 return 0; 92 } 93 94 int board_early_init_f(void) 95 { 96 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 97 98 /* board only uses the DDR_MCK0/1, so disable the DDR_MCK2/3 */ 99 setbits_be32(&gur->ddrclkdr, 0x000f000f); 100 101 return 0; 102 } 103 104 #define CPLD_LANE_A_SEL 0x1 105 #define CPLD_LANE_G_SEL 0x2 106 #define CPLD_LANE_C_SEL 0x4 107 #define CPLD_LANE_D_SEL 0x8 108 109 void board_config_lanes_mux(void) 110 { 111 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 112 int srds_prtcl = (in_be32(&gur->rcwsr[4]) & 113 FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; 114 115 u8 mux = 0; 116 switch (srds_prtcl) { 117 case 0x2: 118 case 0x5: 119 case 0x9: 120 case 0xa: 121 case 0xf: 122 break; 123 case 0x8: 124 mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; 125 break; 126 case 0x14: 127 mux |= CPLD_LANE_A_SEL; 128 break; 129 case 0x17: 130 mux |= CPLD_LANE_G_SEL; 131 break; 132 case 0x16: 133 case 0x19: 134 case 0x1a: 135 mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; 136 break; 137 case 0x1c: 138 mux |= CPLD_LANE_G_SEL | CPLD_LANE_A_SEL; 139 break; 140 default: 141 printf("Fman:Unsupported SerDes Protocol 0x%02x\n", srds_prtcl); 142 break; 143 } 144 CPLD_WRITE(serdes_mux, mux); 145 } 146 147 int board_early_init_r(void) 148 { 149 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 150 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); 151 152 /* 153 * Remap Boot flash + PROMJET region to caching-inhibited 154 * so that flash can be erased properly. 155 */ 156 157 /* Flush d-cache and invalidate i-cache of any FLASH data */ 158 flush_dcache(); 159 invalidate_icache(); 160 161 /* invalidate existing TLB entry for flash + promjet */ 162 disable_tlb(flash_esel); 163 164 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, 165 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 166 0, flash_esel, BOOKE_PAGESZ_256M, 1); 167 168 set_liodns(); 169 setup_portals(); 170 board_config_lanes_mux(); 171 172 return 0; 173 } 174 175 unsigned long get_board_sys_clk(unsigned long dummy) 176 { 177 u8 sysclk_conf = CPLD_READ(sysclk_sw1); 178 179 switch (sysclk_conf & 0x7) { 180 case CPLD_SYSCLK_83: 181 return 83333333; 182 case CPLD_SYSCLK_100: 183 return 100000000; 184 default: 185 return 66666666; 186 } 187 } 188 189 static const char *serdes_clock_to_string(u32 clock) 190 { 191 switch (clock) { 192 case SRDS_PLLCR0_RFCK_SEL_100: 193 return "100"; 194 case SRDS_PLLCR0_RFCK_SEL_125: 195 return "125"; 196 case SRDS_PLLCR0_RFCK_SEL_156_25: 197 return "156.25"; 198 default: 199 return "150"; 200 } 201 } 202 203 #define NUM_SRDS_BANKS 2 204 205 int misc_init_r(void) 206 { 207 serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 208 u32 actual[NUM_SRDS_BANKS]; 209 unsigned int i; 210 u8 sw; 211 static const int freq[][3] = { 212 {0, SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_125}, 213 {SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_156_25, 214 SRDS_PLLCR0_RFCK_SEL_125} 215 }; 216 217 sw = in_8(&CPLD_SW(2)) >> 2; 218 for (i = 0; i < NUM_SRDS_BANKS; i++) { 219 unsigned int clock = (sw >> (2 * i)) & 3; 220 if (clock == 0x3) { 221 printf("Warning: SDREFCLK%u switch setting of '11' is " 222 "unsupported\n", i + 1); 223 break; 224 } 225 if (i == 0 && clock == 0) 226 puts("Warning: SDREFCLK1 switch setting of" 227 "'00' is unsupported\n"); 228 else 229 actual[i] = freq[i][clock]; 230 } 231 232 for (i = 0; i < NUM_SRDS_BANKS; i++) { 233 u32 expected = in_be32(®s->bank[i].pllcr0); 234 expected &= SRDS_PLLCR0_RFCK_SEL_MASK; 235 if (expected != actual[i]) { 236 printf("Warning: SERDES bank %u expects reference clock" 237 " %sMHz, but actual is %sMHz\n", i + 1, 238 serdes_clock_to_string(expected), 239 serdes_clock_to_string(actual[i])); 240 } 241 } 242 243 return 0; 244 } 245 246 void ft_board_setup(void *blob, bd_t *bd) 247 { 248 phys_addr_t base; 249 phys_size_t size; 250 251 ft_cpu_setup(blob, bd); 252 253 base = getenv_bootm_low(); 254 size = getenv_bootm_size(); 255 256 fdt_fixup_memory(blob, (u64)base, (u64)size); 257 258 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 259 fdt_fixup_dr_usb(blob, bd); 260 #endif 261 262 #ifdef CONFIG_PCI 263 pci_of_setup(blob, bd); 264 #endif 265 266 fdt_fixup_liodn(blob); 267 #ifdef CONFIG_SYS_DPAA_FMAN 268 fdt_fixup_fman_ethernet(blob); 269 #endif 270 } 271