1 /*
2  * Copyright 2011 Freescale Semiconductor, Inc.
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20  * MA 02111-1307 USA
21  */
22 
23 #include <common.h>
24 #include <command.h>
25 #include <netdev.h>
26 #include <linux/compiler.h>
27 #include <asm/mmu.h>
28 #include <asm/processor.h>
29 #include <asm/cache.h>
30 #include <asm/immap_85xx.h>
31 #include <asm/fsl_law.h>
32 #include <asm/fsl_serdes.h>
33 #include <asm/fsl_portals.h>
34 #include <asm/fsl_liodn.h>
35 #include <fm_eth.h>
36 
37 extern void pci_of_setup(void *blob, bd_t *bd);
38 
39 #include "cpld.h"
40 
41 DECLARE_GLOBAL_DATA_PTR;
42 
43 int checkboard(void)
44 {
45 	u8 sw;
46 	struct cpu_type *cpu = gd->cpu;
47 	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
48 	unsigned int i;
49 
50 	printf("Board: %sRDB, ", cpu->name);
51 	printf("CPLD version: %d.%d ", CPLD_READ(cpld_ver),
52 			CPLD_READ(cpld_ver_sub));
53 
54 	sw = CPLD_READ(fbank_sel);
55 	printf("vBank: %d\n", sw & 0x1);
56 
57 	/*
58 	 * Display the RCW, so that no one gets confused as to what RCW
59 	 * we're actually using for this boot.
60 	 */
61 	puts("Reset Configuration Word (RCW):");
62 	for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
63 		u32 rcw = in_be32(&gur->rcwsr[i]);
64 
65 		if ((i % 4) == 0)
66 			printf("\n       %08x:", i * 4);
67 		printf(" %08x", rcw);
68 	}
69 	puts("\n");
70 
71 	/*
72 	 * Display the actual SERDES reference clocks as configured by the
73 	 * dip switches on the board.  Note that the SWx registers could
74 	 * technically be set to force the reference clocks to match the
75 	 * values that the SERDES expects (or vice versa).  For now, however,
76 	 * we just display both values and hope the user notices when they
77 	 * don't match.
78 	 */
79 	puts("SERDES Reference Clocks: ");
80 	sw = in_8(&CPLD_SW(2)) >> 2;
81 	for (i = 0; i < 2; i++) {
82 		static const char * const freq[][3] = {{"0", "100", "125"},
83 						{"100", "156.25", "125"}
84 		};
85 		unsigned int clock = (sw >> (2 * i)) & 3;
86 
87 		printf("Bank%u=%sMhz ", i+1, freq[i][clock]);
88 	}
89 	puts("\n");
90 
91 	return 0;
92 }
93 
94 int board_early_init_f(void)
95 {
96 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
97 
98 	/* board only uses the DDR_MCK0/1, so disable the DDR_MCK2/3 */
99 	setbits_be32(&gur->ddrclkdr, 0x000f000f);
100 
101 	return 0;
102 }
103 
104 int board_early_init_r(void)
105 {
106 	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
107 	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
108 
109 	/*
110 	 * Remap Boot flash + PROMJET region to caching-inhibited
111 	 * so that flash can be erased properly.
112 	 */
113 
114 	/* Flush d-cache and invalidate i-cache of any FLASH data */
115 	flush_dcache();
116 	invalidate_icache();
117 
118 	/* invalidate existing TLB entry for flash + promjet */
119 	disable_tlb(flash_esel);
120 
121 	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
122 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
123 			0, flash_esel, BOOKE_PAGESZ_256M, 1);
124 
125 	set_liodns();
126 	setup_portals();
127 
128 	return 0;
129 }
130 
131 unsigned long get_board_sys_clk(unsigned long dummy)
132 {
133 	u8 sysclk_conf = CPLD_READ(sysclk_sw1);
134 
135 	switch (sysclk_conf & 0x7) {
136 	case CPLD_SYSCLK_83:
137 		return 83333333;
138 	case CPLD_SYSCLK_100:
139 		return 100000000;
140 	default:
141 		return 66666666;
142 	}
143 }
144 
145 static const char *serdes_clock_to_string(u32 clock)
146 {
147 	switch (clock) {
148 	case SRDS_PLLCR0_RFCK_SEL_100:
149 		return "100";
150 	case SRDS_PLLCR0_RFCK_SEL_125:
151 		return "125";
152 	case SRDS_PLLCR0_RFCK_SEL_156_25:
153 		return "156.25";
154 	default:
155 		return "150";
156 	}
157 }
158 
159 #define NUM_SRDS_BANKS	2
160 
161 int misc_init_r(void)
162 {
163 	serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
164 	u32 actual[NUM_SRDS_BANKS];
165 	unsigned int i;
166 	u8 sw;
167 	static const int freq[][3] = {
168 		{0, SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_125},
169 		{SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_156_25,
170 			SRDS_PLLCR0_RFCK_SEL_125}
171 	};
172 
173 	sw = in_8(&CPLD_SW(2)) >> 2;
174 	for (i = 0; i < NUM_SRDS_BANKS; i++) {
175 		unsigned int clock = (sw >> (2 * i)) & 3;
176 		if (clock == 0x3) {
177 			printf("Warning: SDREFCLK%u switch setting of '11' is "
178 			       "unsupported\n", i + 1);
179 			break;
180 		}
181 		if (i == 0 && clock == 0)
182 			puts("Warning: SDREFCLK1 switch setting of"
183 				"'00' is unsupported\n");
184 		else
185 			actual[i] = freq[i][clock];
186 	}
187 
188 	for (i = 0; i < NUM_SRDS_BANKS; i++) {
189 		u32 expected = in_be32(&regs->bank[i].pllcr0);
190 		expected &= SRDS_PLLCR0_RFCK_SEL_MASK;
191 		if (expected != actual[i]) {
192 			printf("Warning: SERDES bank %u expects reference clock"
193 			       " %sMHz, but actual is %sMHz\n", i + 1,
194 			       serdes_clock_to_string(expected),
195 			       serdes_clock_to_string(actual[i]));
196 		}
197 	}
198 
199 	return 0;
200 }
201 
202 void ft_board_setup(void *blob, bd_t *bd)
203 {
204 	phys_addr_t base;
205 	phys_size_t size;
206 
207 	ft_cpu_setup(blob, bd);
208 
209 	base = getenv_bootm_low();
210 	size = getenv_bootm_size();
211 
212 	fdt_fixup_memory(blob, (u64)base, (u64)size);
213 
214 #ifdef CONFIG_PCI
215 	pci_of_setup(blob, bd);
216 #endif
217 
218 	fdt_fixup_liodn(blob);
219 #ifdef CONFIG_SYS_DPAA_FMAN
220 	fdt_fixup_fman_ethernet(blob);
221 #endif
222 }
223