1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2011,2012 Freescale Semiconductor, Inc.
4  */
5 
6 #include <common.h>
7 #include <command.h>
8 #include <netdev.h>
9 #include <linux/compiler.h>
10 #include <asm/mmu.h>
11 #include <asm/processor.h>
12 #include <asm/cache.h>
13 #include <asm/immap_85xx.h>
14 #include <asm/fsl_law.h>
15 #include <asm/fsl_serdes.h>
16 #include <asm/fsl_liodn.h>
17 #include <fm_eth.h>
18 
19 extern void pci_of_setup(void *blob, bd_t *bd);
20 
21 #include "cpld.h"
22 
23 DECLARE_GLOBAL_DATA_PTR;
24 
25 int checkboard(void)
26 {
27 	u8 sw;
28 	struct cpu_type *cpu = gd->arch.cpu;
29 	unsigned int i;
30 
31 	printf("Board: %sRDB, ", cpu->name);
32 	printf("CPLD version: %d.%d ", CPLD_READ(cpld_ver),
33 			CPLD_READ(cpld_ver_sub));
34 
35 	sw = CPLD_READ(fbank_sel);
36 	printf("vBank: %d\n", sw & 0x1);
37 
38 	/*
39 	 * Display the actual SERDES reference clocks as configured by the
40 	 * dip switches on the board.  Note that the SWx registers could
41 	 * technically be set to force the reference clocks to match the
42 	 * values that the SERDES expects (or vice versa).  For now, however,
43 	 * we just display both values and hope the user notices when they
44 	 * don't match.
45 	 */
46 	puts("SERDES Reference Clocks: ");
47 	sw = in_8(&CPLD_SW(2)) >> 2;
48 	for (i = 0; i < 2; i++) {
49 		static const char * const freq[][3] = {{"0", "100", "125"},
50 						{"100", "156.25", "125"}
51 		};
52 		unsigned int clock = (sw >> (2 * i)) & 3;
53 
54 		printf("Bank%u=%sMhz ", i+1, freq[i][clock]);
55 	}
56 	puts("\n");
57 
58 	return 0;
59 }
60 
61 int board_early_init_f(void)
62 {
63 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
64 
65 	/* board only uses the DDR_MCK0/1, so disable the DDR_MCK2/3 */
66 	setbits_be32(&gur->ddrclkdr, 0x000f000f);
67 
68 	return 0;
69 }
70 
71 #define CPLD_LANE_A_SEL	0x1
72 #define CPLD_LANE_G_SEL	0x2
73 #define CPLD_LANE_C_SEL	0x4
74 #define CPLD_LANE_D_SEL	0x8
75 
76 void board_config_lanes_mux(void)
77 {
78 	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
79 	int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
80 				FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
81 
82 	u8 mux = 0;
83 	switch (srds_prtcl) {
84 	case 0x2:
85 	case 0x5:
86 	case 0x9:
87 	case 0xa:
88 	case 0xf:
89 		break;
90 	case 0x8:
91 		mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
92 		break;
93 	case 0x14:
94 		mux |= CPLD_LANE_A_SEL;
95 		break;
96 	case 0x17:
97 		mux |= CPLD_LANE_G_SEL;
98 		break;
99 	case 0x16:
100 	case 0x19:
101 	case 0x1a:
102 		mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
103 		break;
104 	case 0x1c:
105 		mux |= CPLD_LANE_G_SEL | CPLD_LANE_A_SEL;
106 		break;
107 	default:
108 		printf("Fman:Unsupported SerDes Protocol 0x%02x\n", srds_prtcl);
109 		break;
110 	}
111 	CPLD_WRITE(serdes_mux, mux);
112 }
113 
114 int board_early_init_r(void)
115 {
116 	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
117 	int flash_esel = find_tlb_idx((void *)flashbase, 1);
118 
119 	/*
120 	 * Remap Boot flash + PROMJET region to caching-inhibited
121 	 * so that flash can be erased properly.
122 	 */
123 
124 	/* Flush d-cache and invalidate i-cache of any FLASH data */
125 	flush_dcache();
126 	invalidate_icache();
127 
128 	if (flash_esel == -1) {
129 		/* very unlikely unless something is messed up */
130 		puts("Error: Could not find TLB for FLASH BASE\n");
131 		flash_esel = 2;	/* give our best effort to continue */
132 	} else {
133 		/* invalidate existing TLB entry for flash + promjet */
134 		disable_tlb(flash_esel);
135 	}
136 
137 	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
138 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
139 			0, flash_esel, BOOKE_PAGESZ_256M, 1);
140 
141 	board_config_lanes_mux();
142 
143 	return 0;
144 }
145 
146 unsigned long get_board_sys_clk(unsigned long dummy)
147 {
148 	u8 sysclk_conf = CPLD_READ(sysclk_sw1);
149 
150 	switch (sysclk_conf & 0x7) {
151 	case CPLD_SYSCLK_83:
152 		return 83333333;
153 	case CPLD_SYSCLK_100:
154 		return 100000000;
155 	default:
156 		return 66666666;
157 	}
158 }
159 
160 #define NUM_SRDS_BANKS	2
161 
162 int misc_init_r(void)
163 {
164 	serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
165 	u32 actual[NUM_SRDS_BANKS];
166 	unsigned int i;
167 	u8 sw;
168 	static const int freq[][3] = {
169 		{0, SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_125},
170 		{SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_156_25,
171 			SRDS_PLLCR0_RFCK_SEL_125}
172 	};
173 
174 	sw = in_8(&CPLD_SW(2)) >> 2;
175 	for (i = 0; i < NUM_SRDS_BANKS; i++) {
176 		unsigned int clock = (sw >> (2 * i)) & 3;
177 		if (clock == 0x3) {
178 			printf("Warning: SDREFCLK%u switch setting of '11' is "
179 			       "unsupported\n", i + 1);
180 			break;
181 		}
182 		if (i == 0 && clock == 0)
183 			puts("Warning: SDREFCLK1 switch setting of"
184 				"'00' is unsupported\n");
185 		else
186 			actual[i] = freq[i][clock];
187 
188 		/*
189 		 * PC board uses a different CPLD with PB board, this CPLD
190 		 * has cpld_ver_sub = 1, and pcba_ver = 5. But CPLD on PB
191 		 * board has cpld_ver_sub = 0, and pcba_ver = 4.
192 		 */
193 		if ((i == 1) && (CPLD_READ(cpld_ver_sub) == 1) &&
194 		    (CPLD_READ(pcba_ver) == 5)) {
195 			/* PC board bank2 frequency */
196 			actual[i] = freq[i-1][clock];
197 		}
198 	}
199 
200 	for (i = 0; i < NUM_SRDS_BANKS; i++) {
201 		u32 expected = in_be32(&regs->bank[i].pllcr0);
202 		expected &= SRDS_PLLCR0_RFCK_SEL_MASK;
203 		if (expected != actual[i]) {
204 			printf("Warning: SERDES bank %u expects reference clock"
205 			       " %sMHz, but actual is %sMHz\n", i + 1,
206 			       serdes_clock_to_string(expected),
207 			       serdes_clock_to_string(actual[i]));
208 		}
209 	}
210 
211 	return 0;
212 }
213 
214 int ft_board_setup(void *blob, bd_t *bd)
215 {
216 	phys_addr_t base;
217 	phys_size_t size;
218 
219 	ft_cpu_setup(blob, bd);
220 
221 	base = env_get_bootm_low();
222 	size = env_get_bootm_size();
223 
224 	fdt_fixup_memory(blob, (u64)base, (u64)size);
225 
226 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
227 	fsl_fdt_fixup_dr_usb(blob, bd);
228 #endif
229 
230 #ifdef CONFIG_PCI
231 	pci_of_setup(blob, bd);
232 #endif
233 
234 	fdt_fixup_liodn(blob);
235 #ifdef CONFIG_SYS_DPAA_FMAN
236 	fdt_fixup_fman_ethernet(blob);
237 #endif
238 
239 	return 0;
240 }
241