1 /* 2 * Copyright 2011 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <netdev.h> 26 #include <linux/compiler.h> 27 #include <asm/mmu.h> 28 #include <asm/processor.h> 29 #include <asm/cache.h> 30 #include <asm/immap_85xx.h> 31 #include <asm/fsl_law.h> 32 #include <asm/fsl_serdes.h> 33 #include <asm/fsl_portals.h> 34 #include <asm/fsl_liodn.h> 35 36 extern void pci_of_setup(void *blob, bd_t *bd); 37 38 #include "cpld.h" 39 40 DECLARE_GLOBAL_DATA_PTR; 41 42 int checkboard(void) 43 { 44 u8 sw; 45 struct cpu_type *cpu = gd->cpu; 46 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 47 unsigned int i; 48 49 printf("Board: %sRDB, ", cpu->name); 50 printf("CPLD version: %d.%d ", CPLD_READ(cpld_ver), 51 CPLD_READ(cpld_ver_sub)); 52 53 sw = CPLD_READ(fbank_sel); 54 printf("vBank: %d\n", sw & 0x1); 55 56 #ifdef CONFIG_PHYS_64BIT 57 puts("36-bit Addressing\n"); 58 #endif 59 60 /* 61 * Display the RCW, so that no one gets confused as to what RCW 62 * we're actually using for this boot. 63 */ 64 puts("Reset Configuration Word (RCW):"); 65 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { 66 u32 rcw = in_be32(&gur->rcwsr[i]); 67 68 if ((i % 4) == 0) 69 printf("\n %08x:", i * 4); 70 printf(" %08x", rcw); 71 } 72 puts("\n"); 73 74 /* 75 * Display the actual SERDES reference clocks as configured by the 76 * dip switches on the board. Note that the SWx registers could 77 * technically be set to force the reference clocks to match the 78 * values that the SERDES expects (or vice versa). For now, however, 79 * we just display both values and hope the user notices when they 80 * don't match. 81 */ 82 puts("SERDES Reference Clocks: "); 83 sw = in_8(&CPLD_SW(2)) >> 2; 84 for (i = 0; i < 2; i++) { 85 static const char * const freq[] = {"0", "100", "125"}; 86 unsigned int clock = (sw >> (2 * i)) & 3; 87 88 printf("Bank%u=%sMhz ", i+1, freq[clock]); 89 } 90 puts("\n"); 91 92 return 0; 93 } 94 95 int board_early_init_f(void) 96 { 97 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 98 99 /* board only uses the DDR_MCK0/1, so disable the DDR_MCK2/3 */ 100 setbits_be32(&gur->ddrclkdr, 0x000f000f); 101 102 return 0; 103 } 104 105 int board_early_init_r(void) 106 { 107 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 108 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); 109 110 /* 111 * Remap Boot flash + PROMJET region to caching-inhibited 112 * so that flash can be erased properly. 113 */ 114 115 /* Flush d-cache and invalidate i-cache of any FLASH data */ 116 flush_dcache(); 117 invalidate_icache(); 118 119 /* invalidate existing TLB entry for flash + promjet */ 120 disable_tlb(flash_esel); 121 122 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, 123 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 124 0, flash_esel, BOOKE_PAGESZ_256M, 1); 125 126 set_liodns(); 127 setup_portals(); 128 129 return 0; 130 } 131 132 static const char *serdes_clock_to_string(u32 clock) 133 { 134 switch (clock) { 135 case SRDS_PLLCR0_RFCK_SEL_100: 136 return "100"; 137 case SRDS_PLLCR0_RFCK_SEL_125: 138 return "125"; 139 case SRDS_PLLCR0_RFCK_SEL_156_25: 140 return "156.25"; 141 default: 142 return "150"; 143 } 144 } 145 146 #define NUM_SRDS_BANKS 2 147 148 int misc_init_r(void) 149 { 150 serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 151 u32 actual[NUM_SRDS_BANKS]; 152 unsigned int i; 153 u8 sw; 154 155 sw = in_8(&CPLD_SW(2)) >> 2; 156 for (i = 0; i < NUM_SRDS_BANKS; i++) { 157 unsigned int clock = (sw >> (2 * i)) & 3; 158 switch (clock) { 159 case 1: 160 actual[i] = SRDS_PLLCR0_RFCK_SEL_100; 161 break; 162 case 2: 163 actual[i] = SRDS_PLLCR0_RFCK_SEL_125; 164 break; 165 default: 166 printf("Warning: SDREFCLK%u switch setting of '11' is " 167 "unsupported\n", i + 1); 168 break; 169 } 170 } 171 172 for (i = 0; i < NUM_SRDS_BANKS; i++) { 173 u32 expected = in_be32(®s->bank[i].pllcr0); 174 expected &= SRDS_PLLCR0_RFCK_SEL_MASK; 175 if (expected != actual[i]) { 176 printf("Warning: SERDES bank %u expects reference clock" 177 " %sMHz, but actual is %sMHz\n", i + 1, 178 serdes_clock_to_string(expected), 179 serdes_clock_to_string(actual[i])); 180 } 181 } 182 183 return 0; 184 } 185 186 void ft_board_setup(void *blob, bd_t *bd) 187 { 188 phys_addr_t base; 189 phys_size_t size; 190 191 ft_cpu_setup(blob, bd); 192 193 base = getenv_bootm_low(); 194 size = getenv_bootm_size(); 195 196 fdt_fixup_memory(blob, (u64)base, (u64)size); 197 198 #ifdef CONFIG_PCI 199 pci_of_setup(blob, bd); 200 #endif 201 202 fdt_fixup_liodn(blob); 203 } 204