1 /* 2 * Copyright 2011 Freescale Semiconductor, Inc. 3 * Author: Mingkai Hu <Mingkai.hu@freescale.com> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* 25 * The RGMII PHYs are provided by the two on-board PHY. The SGMII PHYs 26 * are provided by the three on-board PHY or by the standard Freescale 27 * four-port SGMII riser card. We need to change the phy-handle in the 28 * kernel dts file to point to the correct PHY according to serdes mux 29 * and serdes protocol selection. 30 */ 31 32 #include <common.h> 33 #include <netdev.h> 34 #include <asm/fsl_serdes.h> 35 #include <fm_eth.h> 36 #include <fsl_mdio.h> 37 #include <malloc.h> 38 #include <asm/fsl_dtsec.h> 39 40 #include "cpld.h" 41 #include "../common/fman.h" 42 43 #ifdef CONFIG_FMAN_ENET 44 /* 45 * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means 46 * that the mapping must be determined dynamically, or that the lane maps to 47 * something other than a board slot 48 */ 49 static u8 lane_to_slot[] = { 50 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 2, 2, 2, 2, 0, 0, 0, 0 51 }; 52 53 static int riser_phy_addr[] = { 54 CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR, 55 CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR, 56 CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR, 57 CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR, 58 }; 59 60 /* 61 * Initialize the lane_to_slot[] array. 62 * 63 * On the P2040RDB board the mapping is controlled by CPLD register. 64 */ 65 static void initialize_lane_to_slot(void) 66 { 67 u8 mux = CPLD_READ(serdes_mux); 68 69 lane_to_slot[6] = (mux & SERDES_MUX_LANE_6_MASK) ? 0 : 1; 70 lane_to_slot[10] = (mux & SERDES_MUX_LANE_A_MASK) ? 0 : 2; 71 lane_to_slot[12] = (mux & SERDES_MUX_LANE_C_MASK) ? 0 : 2; 72 lane_to_slot[13] = (mux & SERDES_MUX_LANE_D_MASK) ? 0 : 2; 73 } 74 75 /* 76 * Given the following ... 77 * 78 * 1) A pointer to an Fman Ethernet node (as identified by the 'compat' 79 * compatible string and 'addr' physical address) 80 * 81 * 2) An Fman port 82 * 83 * ... update the phy-handle property of the Ethernet node to point to the 84 * right PHY. This assumes that we already know the PHY for each port. 85 * 86 * The offset of the Fman Ethernet node is also passed in for convenience, but 87 * it is not used, and we recalculate the offset anyway. 88 * 89 * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC. 90 * Inside the Fman, "ports" are things that connect to MACs. We only call them 91 * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs 92 * and ports are the same thing. 93 * 94 */ 95 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, 96 enum fm_port port, int offset) 97 { 98 phy_interface_t intf = fm_info_get_enet_if(port); 99 char phy[16]; 100 101 /* The RGMII PHY is identified by the MAC connected to it */ 102 if (intf == PHY_INTERFACE_MODE_RGMII) { 103 sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC5 ? 0 : 1); 104 fdt_set_phy_handle(fdt, compat, addr, phy); 105 } 106 107 /* The SGMII PHY is identified by the MAC connected to it */ 108 if (intf == PHY_INTERFACE_MODE_SGMII) { 109 int lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + port); 110 u8 slot; 111 if (lane < 0) 112 return; 113 slot = lane_to_slot[lane]; 114 if (slot) { 115 sprintf(phy, "phy_sgmii_%x", 116 CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 117 + (port - FM1_DTSEC1)); 118 fdt_set_phy_handle(fdt, compat, addr, phy); 119 } else { 120 sprintf(phy, "phy_sgmii_%x", 121 CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 122 + (port - FM1_DTSEC1)); 123 fdt_set_phy_handle(fdt, compat, addr, phy); 124 } 125 } 126 127 if (intf == PHY_INTERFACE_MODE_XGMII) { 128 /* XAUI */ 129 int lane = serdes_get_first_lane(XAUI_FM1); 130 if (lane >= 0) { 131 /* The XAUI PHY is identified by the slot */ 132 sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]); 133 fdt_set_phy_handle(fdt, compat, addr, phy); 134 } 135 } 136 } 137 #endif /* #ifdef CONFIG_FMAN_ENET */ 138 139 #define CPLD_LANE_A_SEL 0x1 140 #define CPLD_LANE_G_SEL 0x2 141 #define CPLD_LANE_C_SEL 0x4 142 #define CPLD_LANE_D_SEL 0x8 143 144 int board_eth_init(bd_t *bis) 145 { 146 #ifdef CONFIG_FMAN_ENET 147 struct fsl_pq_mdio_info dtsec_mdio_info; 148 struct tgec_mdio_info tgec_mdio_info; 149 unsigned int i, slot; 150 int lane; 151 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 152 int srds_prtcl = (in_be32(&gur->rcwsr[4]) & 153 FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; 154 u8 mux = CPLD_READ(serdes_mux); 155 156 printf("Initializing Fman\n"); 157 158 initialize_lane_to_slot(); 159 160 dtsec_mdio_info.regs = 161 (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; 162 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; 163 164 /* Register the real 1G MDIO bus */ 165 fsl_pq_mdio_init(bis, &dtsec_mdio_info); 166 167 tgec_mdio_info.regs = 168 (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; 169 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; 170 171 /* Register the real 10G MDIO bus */ 172 fm_tgec_mdio_init(bis, &tgec_mdio_info); 173 174 /* 175 * Program the three on-board SGMII PHY addresses. If the SGMII Riser 176 * card used, we'll override the PHY address later. For any DTSEC that 177 * is RGMII, we'll also override its PHY address later. We assume that 178 * DTSEC4 and DTSEC5 are used for RGMII. 179 */ 180 fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); 181 fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); 182 fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR); 183 184 mux &= ~(CPLD_LANE_A_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL); 185 switch (srds_prtcl) { 186 case 0x2: 187 case 0xf: 188 mux &= ~CPLD_LANE_G_SEL; 189 break; 190 case 0x5: 191 case 0x9: 192 case 0xa: 193 case 0x17: 194 mux |= CPLD_LANE_G_SEL; 195 break; 196 case 0x14: 197 mux = (mux & (~CPLD_LANE_G_SEL)) | CPLD_LANE_A_SEL; 198 break; 199 case 0x8: 200 case 0x16: 201 case 0x19: 202 case 0x1a: 203 mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; 204 break; 205 case 0x1c: 206 mux |= CPLD_LANE_G_SEL | CPLD_LANE_A_SEL; 207 break; 208 default: 209 printf("Fman:Unsupported SerDes Protocol 0x%02x\n", srds_prtcl); 210 break; 211 } 212 CPLD_WRITE(serdes_mux, mux); 213 214 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { 215 int idx = i - FM1_DTSEC1; 216 217 switch (fm_info_get_enet_if(i)) { 218 case PHY_INTERFACE_MODE_SGMII: 219 lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); 220 if (lane < 0) 221 break; 222 slot = lane_to_slot[lane]; 223 if (slot) 224 fm_info_set_phy_address(i, riser_phy_addr[i]); 225 break; 226 case PHY_INTERFACE_MODE_RGMII: 227 /* Only DTSEC4 and DTSEC5 can be routed to RGMII */ 228 fm_info_set_phy_address(i, i == FM1_DTSEC5 ? 229 CONFIG_SYS_FM1_DTSEC5_PHY_ADDR : 230 CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); 231 break; 232 default: 233 printf("Fman1: DTSEC%u set to unknown interface %i\n", 234 idx + 1, fm_info_get_enet_if(i)); 235 break; 236 } 237 238 fm_info_set_mdio(i, 239 miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); 240 } 241 242 lane = serdes_get_first_lane(XAUI_FM1); 243 if (lane >= 0) { 244 slot = lane_to_slot[lane]; 245 if (slot) 246 fm_info_set_phy_address(FM1_10GEC1, 247 CONFIG_SYS_FM1_10GEC1_PHY_ADDR); 248 } 249 250 fm_info_set_mdio(FM1_10GEC1, 251 miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME)); 252 cpu_eth_init(bis); 253 #endif 254 255 return pci_eth_init(bis); 256 } 257